HD64F3664FP datasheet(65/444 Pages) RENESAS

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Section 2 CPU

Rev. 6.00 Mar. 24, 2006 Page 37 of 412

REJ09B0142-0600

(5) Absolute Address—@aa:8, @aa:16, @aa:24

The instruction code contains the absolute address of a memory operand. The absolute address

may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)

For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit

absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the

entire address space.

The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11,

because the upper 8 bits are ignored.

Table 2.11

Absolute Address Access Ranges

Absolute Address

Access Range

8 bits (@aa:8)

H'FF00 to H'FFFF

16 bits (@aa:16)

H'0000 to H'FFFF

24 bits (@aa:24)

H'0000 to H'FFFF

(6) Immediate—#xx:8, #xx:16, or #xx:32

The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an

operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC)

This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the

instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The

PC value to which the displacement is added is the address of the first byte of the next instruction,

so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768

bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an

even number.

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