HD64F3664FP datasheet(26/444 Pages) RENESAS

26 / 444 page

Rev. 6.00 Mar. 24, 2006 Page xxvi of xxviii

Table 7.4

Reprogram Data Computation Table .................................................................... 106

Table 7.5

Additional-Program Data Computation Table...................................................... 106

Table 7.6

Programming Time............................................................................................... 106

Table 7.7

Flash Memory Operating States............................................................................ 111

Section 10 Timer A

Table 10.1

Pin Configuration.................................................................................................. 140

Section 11 Timer V

Table 11.1

Pin Configuration.................................................................................................. 147

Table 11.2

Clock Signals to Input to TCNTV and Counting Conditions ............................... 149

Section 12 Timer W

Table 12.1

Timer W Functions ............................................................................................... 160

Table 12.2

Pin Configuration.................................................................................................. 162

Section 14 Serial Communication Interface 3 (SCI3)

Table 14.1

Pin Configuration.................................................................................................. 198

Table 14.2

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 206

Table 14.2

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 207

Table 14.2

Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 208

Table 14.3

Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 208

Table 14.4

BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 209

Table 14.5

SSR Status Flags and Receive Data Handling ...................................................... 215

Table 14.6

SCI3 Interrupt Requests........................................................................................ 230

Section 15 I2C Bus Interface (IIC)

Table 15.1

I2C Bus Interface Pins........................................................................................... 235

Table 15.2

Communication Format ........................................................................................ 239

Table 15.3

I2C Transfer Rate .................................................................................................. 241

Table 15.4

Flags and Transfer States...................................................................................... 249

Table 15.5

I2C Bus Timing (SCL and SDA Output) .............................................................. 266

Table 15.6

Permissible SCL Rise Time (tsr) Values ............................................................... 267

Table 15.7

I2C Bus Timing (with Maximum Influence of tsr/tsf) ............................................ 268

Section 16 A/D Converter

Table 16.1

Pin Configuration.................................................................................................. 277

Table 16.2

Analog Input Channels and Corresponding ADDR Registers .............................. 278

Table 16.3

A/D Conversion Time (Single Mode)................................................................... 283

Section 17 EEPROM

Table 17.1

Pin Configuration.................................................................................................. 289

Table 17.2

Slave Addresses .................................................................................................... 292

HD64F3664FP Datasheet(PDF) 26 Page - Renesas Technology Corp

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