H83024 datasheet(73/841 Pages) RENESAS

73 / 841 page

Section 2 CPU

Rev. 2.00 Sep 20, 2005 page 35 of 800

REJ09B0260-0200

Table 2.5

Logic Operation Instructions

Instruction Size*

Function

AND

B/W/L

∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general

B/W/L

∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general

XOR

B/W/L

⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another

general register or immediate data.

NOT

B/W/L

¬ Rd

→ Rd

Takes the one’s complement (logical complement) of general register

contents.

Note: * Size refers to the operand size.

B: Byte

W: Word

L: Longword

Table 2.6

Shift Instructions

Instruction Size*

Function

SHAL,

SHAR

B/W/L

Rd (shift)

→ Rd

Performs an arithmetic shift on general register contents.

SHLL,

SHLR

B/W/L

Rd (shift)

→ Rd

Performs a logical shift on general register contents.

ROTL,

ROTR

B/W/L

Rd (rotate)

→ Rd

Rotates general register contents.

ROTXL,

ROTXR

B/W/L

Rd (rotate)

→ Rd

Rotates general register contents, including the carry bit.

Note: * Size refers to the operand size.

B: Byte

W: Word

L: Longword

H83024 Datasheet(PDF) 73 Page - Renesas Technology Corp

H83024 Datasheet(HTML) 73 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL