H83024 datasheet(23/841 Pages) RENESAS

23 / 841 page

Rev. 2.00 Sep 20, 2005 page xxiii of xxxviii

Figures

Section 1 Overview

Figure 1.1

Block Diagram.....................................................................................................

Figure 1.2

Pin Arrangement of H8/3024F-ZTAT, H8/3026F-ZTAT,

H8/3024 Mask ROM Version, and H8/3026 Mask ROM Version

(FP-100B or TFP-100B Package, Top View) ......................................................

Figure 1.3

Pin Arrangement of H8/3024F-ZTAT, H8/3026F-ZTAT,

H8/3024 Mask ROM Version, and H8/3026 Mask ROM Version

(FP-100A Package, Top View)............................................................................

Section 2 CPU

Figure 2.1

CPU Operating Modes.........................................................................................

Figure 2.2

Memory Map .......................................................................................................

Figure 2.3

CPU Registers......................................................................................................

Figure 2.4

Usage of General Registers..................................................................................

Figure 2.5

Stack ....................................................................................................................

Figure 2.6

General Register Data Formats............................................................................

Figure 2.7

General Register Data Formats............................................................................

Figure 2.8

Memory Data Formats .........................................................................................

Figure 2.9

Instruction Formats..............................................................................................

Figure 2.10

Memory-Indirect Branch Address Specification .................................................

Figure 2.11

Processing States .................................................................................................

Figure 2.12

Classification of Exception Sources ....................................................................

Figure 2.13

State Transitions ..................................................................................................

Figure 2.14

Stack Structure after Exception Handling............................................................

Figure 2.15

On-Chip Memory Access Cycle ..........................................................................

Figure 2.16

Pin States during On-Chip Memory Access (Address Update Mode 1)..............

Figure 2.17

Access Cycle for On-Chip Supporting Modules..................................................

Figure 2.18

Pin States during Access to On-Chip Supporting Modules .................................

Section 3 MCU Operating Modes

Figure 3.1

Memory Map of H8/3024F-ZTAT and H8/3024 Mask ROM Version in Each

Operating Mode ...................................................................................................

Figure 3.2

Memory Map of H8/3026F-ZTAT and H8/3026 Mask ROM Version in Each

Operating Mode ...................................................................................................

Section 4 Exception Handling

Figure 4.1

Exception Sources ...............................................................................................

Figure 4.2

Reset Sequence (Modes 1 and 3) .........................................................................

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