H83024 datasheet(30/841 Pages) RENESAS

30 / 841 page

Rev. 2.00 Sep 20, 2005 page xxx of xxxviii

Figure 17.16 Power-On/Off Timing (Boot Mode).................................................................... 523

Figure 17.17 Power-On/Off Timing (User Program Mode) ..................................................... 524

Figure 17.18 Mode Transition Timing

(Example: Boot Mode

→ User Mode ↔ User Program Mode) .......................... 525

Figure 17.19 ROM Block Diagram (H8/3026 Mask ROM Version)........................................ 526

Figure 17.20 Mask ROM Addresses and Data.......................................................................... 527

Section 18 Flash Memory [H8/3024F-ZTAT Version]

Figure 18.1

Block Diagram of Flash Memory ........................................................................ 531

Figure 18.2

Example of ROM Area/RAM Area Overlap ....................................................... 541

Figure 18.3

Flash Memory Related State Transitions ............................................................. 542

Figure 18.4

Reading Overlap RAM Data in User Mode/User Program Mode ....................... 545

Figure 18.5

Writing Overlap RAM Data in User Program Mode ........................................... 546

Figure 18.6

System Configuration When Using Boot Mode .................................................. 548

Figure 18.7

Boot Mode Execution Procedure ......................................................................... 549

Figure 18.8

RAM Areas in Boot Mode................................................................................... 551

Figure 18.9

Example of User Program Mode Execution Procedure ....................................... 554

Figure 18.10 FLMCR1 Bit Settings and State Transitions ....................................................... 556

Figure 18.11 Program/Program-Verify Flowchart (128-Byte Programming)........................... 561

Figure 18.12 Erase/Erase-Verify Flowchart (Single-Block Erasing) ........................................ 564

Figure 18.13 Flash Memory State Transitions (When High Level is Applied to FWE Pin

in Mode 5 or 7 (On-Chip ROM Enabled))........................................................... 568

Figure 18.14 Example of RAM Overlap Operation .................................................................. 569

Figure 18.15 Memory Map in PROM Mode............................................................................. 572

Figure 18.16 Power-On/Off Timing (Boot Mode).................................................................... 576

Figure 18.17 Power-On/Off Timing (User Program Mode) ..................................................... 577

Figure 18.18 Mode Transition Timing

(Example: Boot Mode

→ User Mode ↔ User Program Mode) .......................... 578

Section 19 Clock Pulse Generator

Figure 19.1

Block Diagram of Clock Pulse Generator ........................................................... 582

Figure 19.2

Connection of Crystal Resonator (Example) ....................................................... 583

Figure 19.3

Crystal Resonator Equivalent Circuit .................................................................. 584

Figure 19.4

Oscillator Circuit Block Board Design Precautions ............................................ 584

Figure 19.5

External Clock Input (Examples) ........................................................................ 585

Figure 19.6

External Clock Input Timing ............................................................................... 587

Figure 19.7

External Clock Output Settling Delay Timing..................................................... 587

Section 20 Power-Down State

Figure 20.1

NMI Timing for Software Standby Mode (Example).......................................... 601

Figure 20.2

Hardware Standby Mode Timing......................................................................... 603

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