SH7046 datasheet(55/611 Pages) RENESAS

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Section 2 CPU

Rev. 4.00 Dec 05, 2005 page 11 of 564

REJ09B0270-0400

2.2.2

Control Registers

The control registers consist of three 32-bit registers: status register (SR), global base register

(GBR), and vector base register (VBR). The status register indicates processing states. The global

base register functions as a base address for the indirect GBR addressing mode to transfer data to

the registers of on-chip peripheral modules. The vector base register functions as the base address

of the exception processing vector area (including interrupts).

Status Register (SR):

Bit

Bit Name

Initial

Value

R/W

Description

31 to



All 0

R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

Undefined

R/W

Used by the DIV0U, DIV0S, and DIV1 instructions.

Undefined

R/W

Used by the DIV0U, DIV0S, and DIV1 instructions.

7 to 4

I3 to I0

All 1

R/W

Interrupt mask bits.

3, 2



All 0

R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

Undefined

R/W

S bit

Used by the MAC instruction.

Undefined

R/W

T bit

The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF

(BF/S), SETT, and CLRT instructions use the T bit to

indicate true (1) or false (0).

The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S,

DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR,

ROTL, ROTCR, and ROTCL instructions also use the

T bit to indicate carry/borrow or overflow/underflow.

Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode.

The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register

areas and in logic operations.

Vector Base Register (VBR): Indicates the base address of the exception processing vector area.

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