SH7046 datasheet(28/611 Pages) RENESAS

28 / 611 page

Rev. 4.00 Dec 05, 2005 page xxviii of xliv

15.7

Usage Notes ...................................................................................................................... 422

15.7.1 Module Standby Mode Setting ............................................................................ 422

15.7.2 Notes for MMT Operation ................................................................................... 422

15.8

Port Output Enable (POE)................................................................................................. 426

15.8.1 Features................................................................................................................ 426

15.8.2 Input/Output Pins ................................................................................................. 427

15.8.3 Register Description............................................................................................. 427

15.8.4 Operation ............................................................................................................. 430

15.8.5 Usage Note........................................................................................................... 431

Section 16 Pin Function Controller (PFC) ................................................................... 433

16.1

Register Descriptions ........................................................................................................ 438

16.1.1 Port A I/O Register L (PAIORL) ......................................................................... 439

16.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)................................. 439

16.1.3 Port B I/O Register (PBIOR) ............................................................................... 442

16.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)...................................... 443

16.1.5 Port E I/O Registers L and H (PEIORL and PEIORH)........................................ 444

16.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) ....... 445

16.2

Usage Notes ...................................................................................................................... 448

Section 17 I/O Ports ............................................................................................................ 449

17.1

Port A ................................................................................................................................ 449

17.1.1 Register Description............................................................................................. 450

17.1.2 Port A Data Register L (PADRL) ........................................................................ 450

17.2

Port B ................................................................................................................................ 451

17.2.1 Register Descriptions ........................................................................................... 451

17.2.2 Port B Data Register (PBDR) .............................................................................. 452

17.3

Port E ................................................................................................................................ 453

17.3.1 Register Descriptions ........................................................................................... 454

17.3.2 Port E Data Registers H and L (PEDRH and PEDRL) ........................................ 454

17.4

Port F................................................................................................................................. 456

17.4.1 Register Description............................................................................................. 456

17.4.2 Port F Data Register (PFDR) ............................................................................... 456

17.5

Port G ................................................................................................................................ 457

17.5.1 Register Description............................................................................................. 458

17.5.2 Port G Data Register (PGDR) .............................................................................. 458

Section 18 Flash Memory (F-ZTAT Version) ............................................................ 459

18.1

Features ............................................................................................................................. 459

18.2

Mode Transitions .............................................................................................................. 460

18.3

Block Configuration.......................................................................................................... 464

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