SH7046 datasheet(22/611 Pages) RENESAS

22 / 611 page

Rev. 4.00 Dec 05, 2005 page xxii of xliv

Section 8 Data Transfer Controller (DTC)................................................................... 105

8.1

Features ............................................................................................................................. 105

8.2

Register Descriptions ........................................................................................................ 107

8.2.1

DTC Mode Register (DTMR).............................................................................. 108

8.2.2

DTC Source Address Register (DTSAR)............................................................. 110

8.2.3

DTC Destination Address Register (DTDAR)..................................................... 110

8.2.4

DTC Initial Address Register (DTIAR) ............................................................... 110

8.2.5

DTC Transfer Count Register A (DTCRA) ......................................................... 110

8.2.6

DTC Transfer Count Register B (DTCRB).......................................................... 110

8.2.7

DTC Enable Registers (DTER)............................................................................ 111

8.2.8

DTC Control/Status Register (DTCSR)............................................................... 112

8.2.9

DTC Information Base Register (DTBR) ............................................................ 113

8.3

Operation .......................................................................................................................... 113

8.3.1

Activation Sources ............................................................................................... 113

8.3.2

Location of Register Information and DTC Vector Table ................................... 114

8.3.3

DTC Operation .................................................................................................... 117

8.3.4

Interrupt Source ................................................................................................... 123

8.3.5

Operation Timing................................................................................................. 123

8.3.6

DTC Execution State Counts ............................................................................... 124

8.4

Procedures for Using DTC................................................................................................ 125

8.4.1

Activation by Interrupt......................................................................................... 125

8.4.2

Activation by Software ........................................................................................ 125

8.4.3

DTC Use Example ............................................................................................... 126

8.5

Cautions on Use ................................................................................................................ 127

8.5.1

Prohibition against DTC Register Access by DTC .............................................. 127

8.5.2

Module Standby Mode Setting ............................................................................ 127

8.5.3

On-Chip RAM ..................................................................................................... 127

Section 9 Bus State Controller (BSC) ........................................................................... 129

9.1

Features ............................................................................................................................. 129

9.2

Input/Output Pin................................................................................................................ 129

9.3

Register Configuration ...................................................................................................... 129

9.4

Register Descriptions ........................................................................................................ 131

9.4.1

Bus Control Register 1 (BCR1) ........................................................................... 131

9.4.2

RAM Emulation Register (RAMER)................................................................... 131

9.5

Bus Arbitration.................................................................................................................. 132

9.6

On-chip Peripheral I/O Register Access ........................................................................... 132

Section 10 Multi-Function Timer Pulse Unit (MTU) ............................................... 133

10.1

Features ............................................................................................................................. 133

10.2

Input/Output Pins .............................................................................................................. 137

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