SH7660 datasheet(13/846 Pages) RENESAS

13 / 846 page

Rev. 1.00, 02/04, page xiii of xxxviii

9.4.7

Refresh Time Constant Register (RTCOR) ......................................................... 247

9.4.8

Reset Wait Counter (RWTCNT).......................................................................... 247

9.5

Operating Description ....................................................................................................... 248

9.5.1

Endian/Access Size and Data Alignment............................................................. 248

9.5.2

Normal Space Interface........................................................................................ 251

9.5.3

Access Wait Control ............................................................................................ 256

9.5.4

CSn Assert Period Expansion ..............................................................................258

9.5.5

SDRAM Interface ................................................................................................ 259

9.5.6

Burst ROM Interface ........................................................................................... 285

9.5.7

Byte-Selection SRAM Interface .......................................................................... 287

9.5.8

Wait between Access Cycles ............................................................................... 291

9.5.9

Bus Arbitration .................................................................................................... 291

9.5.10 Usage Notes ......................................................................................................... 295

Section 10 Direct Memory Access Controller (DMAC) ...................................297

10.1

Features............................................................................................................................. 297

10.2

Input/Output Pins .............................................................................................................. 299

10.3

Register Descriptions ........................................................................................................ 300

10.3.1 DMA Source Address Register (SAR) ................................................................ 301

10.3.2 DMA Destination Address Register (DAR) ........................................................ 301

10.3.3 DMA Transfer Count Register (DMATCR) ........................................................ 301

10.3.4 DMA Channel Control Register (CHCR) ............................................................ 302

10.3.5 DMA Initial Address Register (IAR)................................................................... 308

10.3.6 DMA Operation Register (DMAOR) .................................................................. 308

10.3.7 DMA Extension Resource Selector 0 and 1 (DMARS0 and DMARS1) ............. 310

10.4

Operation .......................................................................................................................... 313

10.4.1 DMA Transfer Flow ............................................................................................ 313

10.4.2 Repeat Mode Transfer.......................................................................................... 315

10.4.3 DMA Transfer Requests ...................................................................................... 315

10.4.4 Channel Priority................................................................................................... 318

10.4.5 DMA Transfer Types........................................................................................... 321

10.4.6 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 328

10.5

Usage Notes ...................................................................................................................... 332

Section 11 Clock Pulse Generator (CPG)..........................................................333

11.1

Features............................................................................................................................. 333

11.2

Input/Output Pins .............................................................................................................. 336

11.3

Clock Operating Modes .................................................................................................... 337

11.4

Register Descriptions ........................................................................................................ 340

11.4.1 Frequency Control Register (FRQCR) ................................................................ 340

11.5

Changing the Frequency ................................................................................................... 343

11.5.1 Changing the Multiplication Rate ........................................................................ 343

11.5.2 Changing the Division Ratio................................................................................ 343

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