SH7660 datasheet(30/846 Pages) RENESAS

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Rev. 1.00, 02/04, page xxx of xxxviii

Figure 28.25 Burst Read Bus Cycle of Synchronous DRAM (Single Read

× 4)

(Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 2 Cycle) ........ 755

Figure 28.26 Burst Read Bus Cycle of Synchronous DRAM (Single Read

× 4)

(Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycle, TRP = 1 Cycle) ........ 756

Figure 28.27 Single Write Bus Cycle of Synchronous DRAM

(Auto Precharge Mode, TRWL = 1 Cycle)............................................................ 757

Figure 28.28 Single Write Bus Cycle of Synchronous DRAM

(Auto Precharge Mode, TRCD = 3 Cycle, TRWL = 1 Cycle) .............................. 758

Figure 28.29 Burst Write Bus Cycle of Synchronous DRAM (Single Write

× 4)

(Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) .............................. 759

Figure 28.30 Burst Write Bus Cycle of Synchronous DRAM (Single Write

× 4)

(Auto Precharge Mode, TRCD = 1 Cycle, TRWL = 1 Cycle) .............................. 760

Figure 28.31 Burst Read Bus Cycle of Synchronous DRAM (Single Read

× 4)

(Bank Active Mode: ACTV + READ Command, CAS Latency 2,

TRCD = 1 Cycle)................................................................................................... 761

Figure 28.32 Burst Read Bus Cycle of Synchronous DRAM (Single Read

× 4)

(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2,

TRCD = 1 Cycle)................................................................................................... 762

Figure 28.33 Burst Read Bus Cycle of Synchronous DRAM (Single Read

× 4)

(Bank Active Mode: PRE + ACTV + READ Command, Different Row Address,

CAS Latency 2, TRCD = 1 Cycle) ........................................................................ 763

Figure 28.34 Burst Write Bus Cycle of Synchronous DRAM (Single Write

× 4)

(Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................... 764

Figure 28.35 Burst Write Bus Cycle of Synchronous DRAM (Single Write

× 4)

(Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................... 765

Figure 28.36 Burst Write Bus Cycle of Synchronous DRAM (Single Write

× 4)

(Bank Active Mode: PRE + ACTV + WRIT Command, TRCD = 1 Cycle)......... 766

Figure 28.37 Auto Refresh Timing of Synchronous DRAM (TRP = 2 Cycle) .......................... 767

Figure 28.38 Self Refresh Timing of Synchronous DRAM (TRP = 2 Cycle) ............................ 768

Figure 28.39 Power-On Sequence of Synchronous DRAM

(Mode Write Timing, TRP = 2 Cycle)................................................................... 769

Figure 28.40 Access Timing in Low-Frequency Mode of Synchronous DRAM

(Auto Precharge Mode, TRWL = 1 Cycle)............................................................ 770

Figure 28.41 Auto Refresh Timing in Low-Frequency Mode of Synchronous DRAM

(TRP = 2 Cycle)..................................................................................................... 771

Figure 28.42 Self Refresh Timing in Low-Frequency Mode of Synchronous DRAM

(TRP = 2 Cycle)..................................................................................................... 772

Figure 28.43 Power-On Sequence in Low-Frequency Mode of Synchronous DRAM

(Mode Write Timing, TRP = 2 Cycle)................................................................... 773

Figure 28.44 Write to Read Bus Cycle in Power-Down Mode of Synchronous DRAM

(Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)..... 774

Figure 28.45 Read to Write Bus Cycle in Power-Down Mode of Synchronous DRAM

(Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)..... 775

SH7660 Datasheet(PDF) 30 Page - Renesas Technology Corp

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