7540 datasheet(339/366 Pages) RENESAS

339 / 366 page

3-117

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

APPENDIX

3.5 List of registers

Fig. 3.5.34 Structure of CPU mode register

b7b6b5b4b3b2b1b0

Function

At reset

Name

CPU mode register (CPUM) [Address : 3B16]

CPU mode register

0 0 : Single-chip mode

0 1 : Not available

1 0 : Not available

1 1 : Not available

b1 b0

Processor mode bits (Note 1)

0 : Ceramic oscillation

1 : RC oscillation

0 : 0 page

1 : 1 page

Stack page selection bit

Oscillation mode selection bit

(Note 1)

Clock division ratio selection

bits

0 0 :

φ = f(XIN)/2

(high-speed mode)

0 1 :

φ = f(XIN)/8

(middle-speed mode)

1 0 : Applied from on-chip oscillator

1 1 :

φ = f(XIN)

(double-speed mode)

(Note 2)

b7 b6

0 : Ceramic or RC oscillation enabled

1 : Ceramic or RC oscillation stop

Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is

disable to write any data to the bit. However, by reset the bit is initialized and

can be rewritten, again.

(It is not disable to write any data to the bit for emulator MCU “M37540RSS”.)

2: These bits are used only when a ceramic oscillation is selected.

Do not use these when an RC oscillation is selected.

On-chip oscillator oscillation

control bit

0 : On-chip oscillator oscillation enabled

1 : On-chip oscillator oscillation stop

XIN oscillation control bit

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