7540 datasheet(332/366 Pages) RENESAS

332 / 366 page

3-110

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

APPENDIX

7540 Group

3.5 List of registers

Fig. 3.5.22 Structure of Timer X mode register

Timer X operating modes

Timer mode

Pulse output mode

Event counter mode

Pulse width measurement mode

CNTR0 active edge switch bit (bit 2 of address 2B16) contents

“0” CNTR0 interrupt request occurrence: Falling edge

; No influence to timer count

“1” CNTR0 interrupt request occurrence: Rising edge

; No influence to timer count

“0” Pulse output start: Beginning at “H” level

CNTR0 interrupt request occurrence: Falling edge

“1” Pulse output start: Beginning at “L” level

CNTR0 interrupt request occurrence: Rising edge

“0” Timer X: Rising edge count

CNTR0 interrupt request occurrence: Falling edge

“1” Timer X: Falling edge count

CNTR0 interrupt request occurrence: Rising edge

“0” Timer X: “H” level width measurement

CNTR0 interrupt request occurrence: Falling edge

“1” Timer X: “L” level width measurement

CNTR0 interrupt request occurrence: Rising edge

Table 3.5.2 CNTR0 active edge switch bit function

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

Timer X mode register (TXM) [Address : 2B 16]

Nothing is allocated for these bits. These are write disabled bits.

When these bits are read out, the values are “0”.

Timer X mode register

0 0 : Timer mode

0 1 : Pulse output mode

1 0 : Event counter mode

1 1 : Pulse width measurement

mode

b1 b0

Timer X operating mode bits

CNTR0 active edge switch bit

The function depends on the

operating mode.

(Refer to Table 3.5.2)

Timer X count stop bit

0 : Count start

1 : Count stop

0 : Output invalid (I/O port)

1 : Output valid (Inverted CNTR 0

output)

P03/TXOUT output valid bit

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