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SH7763 Datasheet(PDF) 55 Page - Renesas Technology Corp

Part # SH7763
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series
PDF  2026 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7763 Datasheet(HTML) 55 Page - Renesas Technology Corp

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Rev. 1.00 Oct. 01, 2007 Page lv of lxvi
Figure 43.23 MPX Basic Bus Cycle: Write.............................................................................. 1853
Figure 43.24 MPX Bus Cycle: Burst Read............................................................................... 1854
Figure 43.25 MPX Bus Cycle: Burst Write .............................................................................. 1855
Figure 43.26 Byte Control SRAM Bus Cycle .......................................................................... 1856
Figure 43.27 Byte Control SRAM Bus Cycle: Basic Read Cycle (No Wait, No Address
Setup/Hold Time Insertion, RDS = 1, RDH = 0) ................................................ 1857
Figure 43.28 DDRIF MCLK Output Timing............................................................................ 1859
Figure 43.29 Read Timing of DDR-SDRAM (2 Burst Read) .................................................. 1859
Figure 43.30 Write Timing of DDR-SDRAM (2 Burst Write)................................................. 1860
Figure 43.31 NMI Input Timing ............................................................................................... 1861
Figure 43.32 IRQ/
IRL, PINT Input and IRQOUT Output Timing...........................................1862
Figure 43.33 External CPU Interface Read/Write Access Timing ........................................... 1864
Figure 43.34 PCI Clock Input Timing ...................................................................................... 1866
Figure 46.35 Output Signal Timing.......................................................................................... 1866
Figure 43.36 Input Signal Timing............................................................................................. 1866
Figure 43.37
DREQ, TEND, and DACK Timing.....................................................................1867
Figure 43.38 TCLK Input Timing ............................................................................................ 1868
Figure 43.39 TPU Output Timing............................................................................................. 1869
Figure 43.40 TPU Clock Input Timing..................................................................................... 1869
Figure 43.41 MII Transmit Timing (normal operation)............................................................ 1871
Figure 43.42 MII Receive Timing (normal operation) ............................................................. 1871
Figure 43.43 MII Receive Timing (When an Error is Detected) .............................................. 1872
Figure 43.44 WOL Output Timing ........................................................................................... 1872
Figure 43.45 GMII Transmit Timing (normal operation)......................................................... 1873
Figure 43.46 GMII Receive Timing (normal operation) .......................................................... 1873
Figure 43.47 GMII Receive Timing (When an Error is Detected) ........................................... 1874
Figure 43.48 WOL Output Timing ........................................................................................... 1874
Figure 43.49 RMII Transmit Timing........................................................................................ 1875
Figure 43.50 RMII Receive Timing (normal operation)........................................................... 1875
Figure 43.51 RMII Receive Timing (When an Error is Detected)............................................ 1876
Figure 43.52 STIF Clock Valid Receive Timing...................................................................... 1877
Figure 43.53 STIF Clock Valid Transmit Timing .................................................................... 1878
Figure 43.54 STIF Strobe Receive Timing............................................................................... 1878
Figure 43.55 STIF Strobe Transmit Timing ............................................................................. 1879
Figure 43.56 I2C Bus Interface Input/Output Timing ............................................................... 1881
Figure 43.57 AC Characteristic Load Condition ...................................................................... 1881
Figure 43.58 SCIFn_SCK Input Clock Timing ........................................................................ 1882
Figure 43.59 SCIFn I/O Synchronous Mode Clock Timing ..................................................... 1883
Figure 43.60 SIOF_MCLK Input Timing................................................................................. 1884



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