SH7763 datasheet(30/2026 Pages) RENESAS

30 / 2026 page

Rev. 1.00 Oct. 01, 2007 Page xxx of lxvi

34.3.2 Status Register (SSISR) ...................................................................................... 1431

34.3.3 Transmit Data Register (SSITDR)...................................................................... 1436

34.3.4 Receive Data Register (SSIRDR) ....................................................................... 1436

34.4

Operation ......................................................................................................................... 1437

34.4.1 Bus Format ......................................................................................................... 1437

34.4.2 Non-Compressed Modes..................................................................................... 1438

34.4.3 Operation Modes ................................................................................................ 1448

34.4.4 Transmit Operation ............................................................................................. 1449

34.4.5 Receive Operation .............................................................................................. 1452

34.4.6 Serial Clock Control ........................................................................................... 1455

34.5

Usage Note....................................................................................................................... 1456

34.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation .......... 1456

34.5.2 Restrictions for Operation in Slave Mode........................................................... 1456

Section 35 USB Host Controller (USBH) ....................................................... 1457

35.1

Features............................................................................................................................ 1457

35.2

Pin Description ................................................................................................................ 1459

35.3

Register Description ........................................................................................................ 1460

35.3.1 HcRevision Register (USBHR) .......................................................................... 1462

35.3.2 HcControl Register (USBHC) ............................................................................ 1463

35.3.3 HcCommandStatus Register (USBHCS) ............................................................ 1465

35.3.4 HcInterruptStatus Register (USBHIS) ................................................................ 1466

35.3.5 HcInterruptEnable Register (USBHIE) .............................................................. 1468

35.3.6 HcInterruptDisable Register (USBHID)............................................................. 1469

35.3.7 HcHCCA Register (USBHHCCA) ..................................................................... 1471

35.3.8 HcPeriodCurrentED Register (USBHPCED) ..................................................... 1471

35.3.9 HcControlHeadED Register (USBHCHED) ...................................................... 1472

35.3.10 HcControlCurrentED Register (USBHCCED) ................................................... 1472

35.3.11 HcBulkHeadED Register (USBHBHED)........................................................... 1473

35.3.12 HcBulkCurrentED Register (USBHBCED) ....................................................... 1473

35.3.13 HcDoneHead Register (USBHDHED) ............................................................... 1474

35.3.14 HcFmInterval Register (USBHFI)...................................................................... 1475

35.3.15 HcFrameRemaining Register (USBHFR)........................................................... 1476

35.3.16 HcFmNumber Register (USBHFN).................................................................... 1477

35.3.17 HcPeriodicStart Register (USBHPS) .................................................................. 1478

35.3.18 HcLSThreshold Register (USBHLST) (Not supporting LowSpeed mode) ........ 1479

35.3.19 HcRhDescriptorA Register (USBHRDA)

(Only one port is supported by this LSI.)............................................................ 1480

35.3.20 HcRhDescriptorB Register (USBHRDB)

(Only one port is supported by this LSI.)............................................................ 1482

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