SH7763 datasheet(32/2026 Pages) RENESAS

32 / 2026 page

Rev. 1.00 Oct. 01, 2007 Page xxxii of lxvi

36.3.27 Trigger Register (TRG) ...................................................................................... 1536

36.3.28 Data Status Register (DASTS)............................................................................ 1537

36.3.29 FIFO Clear Register 0 (FCLR0) ......................................................................... 1538

36.3.30 FIFO Clear Register 1 (FCLR1) ......................................................................... 1539

36.3.31 DMA Transfer Setting Register (DMA) ............................................................. 1540

36.3.32 Endpoint Stall Register 0 (EPSTL0)................................................................... 1541

36.3.33 Endpoint Stall Register 1 (EPSTL1)................................................................... 1542

36.3.34 Configuration Value Register (CVR) ................................................................. 1543

36.3.35 Time Stamp Register (TSRH/TSRL).................................................................. 1544

36.3.36 Control Register 0 (CTLR0) ............................................................................... 1546

36.3.37 Control Register 1 (CTLR1) ............................................................................... 1548

36.3.38 Endpoint Information Register (EPIR) ............................................................... 1549

36.3.39 Timer Register (TMRH/TMRL) ......................................................................... 1555

36.3.40 Set Time Out Register (STOH/STOL) ............................................................... 1557

36.4

Operation ......................................................................................................................... 1559

36.4.1 Cable Connection................................................................................................ 1559

36.4.2 Cable Disconnection ........................................................................................... 1560

36.4.3 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................. 1566

36.4.4 EP2 Bulk-In Transfer (Dual FIFOs) ................................................................... 1567

36.4.5 EP3 Interrupt-In Transfer.................................................................................... 1569

36.5

EP4 Isochronous-Out Transfer......................................................................................... 1570

36.6

EP5 Isochronous-In Transfer ........................................................................................... 1573

36.7

Processing of USB Standard Commands and Class/Vendor Commands ........................ 1576

36.7.1 Processing of Commands Transmitted by Control Transfer ............................... 1576

36.8

Stall Operations................................................................................................................ 1577

36.8.1 Overview ............................................................................................................ 1577

36.8.2 Forcible Stall by Application .............................................................................. 1577

36.8.3 Automatic Stall by USB Function Controller ..................................................... 1579

36.9

Examples of External Circuit........................................................................................... 1581

36.9.1 Example of the Connection between USB Function Controller ......................... 1581

36.10 Usage Notes ..................................................................................................................... 1582

36.10.1 Setup Data Reception ......................................................................................... 1582

36.10.2 FIFO Clear .......................................................................................................... 1582

36.10.3 Overreading/Overwriting of Data Register......................................................... 1582

36.10.4 Assigning EP0 Interrupt Sources ........................................................................ 1583

36.10.5 FIFO Clear when DMA Transfer is Set .............................................................. 1583

36.10.6 Note on Using TR Interrupt ................................................................................ 1583

SH7763 Datasheet(PDF) 32 Page - Renesas Technology Corp

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