SH77640 datasheet(19/1752 Pages) RENESAS

19 / 1752 page

Rev. 1.00 Nov. 22, 2007 Page xix of lvi

17.3.8 Descriptor Table ................................................................................................... 602

17.3.9 Termination Flag and Descriptor DMA Start Address ......................................... 603

17.3.10 Descriptor DMA Transfer Count .......................................................................... 604

17.3.11 DMA Start Address Register (ATAPI_DMA_START_ADR)............................. 605

17.3.12 DMA Transfer Count Register (ATAPI_DMA_TRANS_CNT) .......................... 606

17.3.13 ATAPI Control 2 (ATAPI_CONTROL2) ............................................................ 607

17.3.14 ATAPI Signal Status Register (ATAPI_SIG_ST) ................................................ 608

17.3.15 Byteswap (ATAPI_BYTE_SWAP)...................................................................... 609

17.3.16 ATAPI Data Bus Alignment ................................................................................. 610

17.4

Functional Description....................................................................................................... 611

17.4.1 Data Transfer Modes ............................................................................................ 611

17.4.2 Descriptor Function .............................................................................................. 611

17.5

Operating Procedure .......................................................................................................... 612

17.5.1 Initialization .......................................................................................................... 612

17.5.2 Procedure in PIO Transfer Mode .......................................................................... 612

17.5.3 Procedure in Multiword DMA Transfer Mode ..................................................... 613

17.5.4 Procedure in Ultra DMA Transfer Mode .............................................................. 616

17.5.5 Procedure in Hardware Reset for ATAPI Device ................................................. 617

Section 18 Serial Sound Interface (SSI) ............................................................619

18.1

Features.............................................................................................................................. 619

18.1.1 SSI Module Configuration.................................................................................... 619

18.1.2 SSI Features .......................................................................................................... 619

18.2

Input/Output Pins ...............................................................................................................621

18.3

Register Descriptions ......................................................................................................... 621

18.3.1 DMA Mode Registers 0 to 5 (SSIDMMR0 to SSIDMMR5)................................ 633

18.3.2 RDMA Transfer Source Address Registers 0 to 5

(SSIRDMADR0 to SSIRDMADR5) .................................................................... 634

18.3.3 RDMA Transfer Word Count Registers 0 to 5

(SSIRDMCNTR0 to SSIRDMCNTR5)................................................................ 635

18.3.4 WDMA Transfer Destination Address Registers 0 to 5

(SSIWDMADR0 to SSIWDMADR5) .................................................................. 637

18.3.5 WDMA Transfer Word Count Registers 0 to 5

(SSIWDMCNTR0 to SSIWDMCNTR5).............................................................. 637

18.3.6 DMA Control Registers 0 to 5 (SSIDMCOR0 to SSIDMCOR5)......................... 638

18.3.7 Transmit Suspension Block Counters 0 to 5

(SSISTPBLCNT0 to SSISTPBLCNT5) ............................................................... 649

18.3.8 Transmit Suspension Transfer Data Registers 0 to 5

(SSISTPDR0 to SSISTPDR5) .............................................................................. 650

18.3.9 Block Count Source Registers 0 to 5 (SSIBLCNTSR0 to SSIBLCNTSR5) ........ 651

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