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7220 Datasheet(PDF) 176 Page - Renesas Technology Corp |
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7220 Datasheet(HTML) 176 Page - Renesas Technology Corp |
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176 / 303 page ![]() APPLICATION 5.1 Example of multi-line display 5-3 7220 Group User’s Manual 5.1.3 General flowchart The multi-line display processing routine consists of initialization processing routine, VSYNC interrupt processing routine, and CRT interrupt processing routine. (1) Initialization processing routine This routine is used to initialize to cause a CRT interrupt. Fig. 5.1.3 Flowchart of initialization processing routine CS (address 00E4 16) MD (address 00E5 16) HR (address 00E0 16) CK (address 00ED 16) Multi-line display start END CV2 (address 00E2 16) ← Vertical display start position of the 12th line (block 2) Line counter F_VSYNC Block 1 display RAM ← Display character (blank) of block 1 (addresses 0600 16 to 061716) Character color (no output) of block 1 (addresses 0680 16 to 069716) Enable CRT interrupt in synchronized with the next V SYNC Character size : minimum size Border output Set a horizontal display start position Set display clock Disable only CRT interrupt All blocks display off Select R/G/B/OUT1 HSYNC/VSYNC input polarity : positive polarity input R/G/B/OUT1 output polarity : positive polarity output Color register 0 : red Color register 1 : blue Color register 2 : white Color register 3 : cyan ←“000000002” ←“000001012” ←“XXXXXXXX2” ←“000000102” Counter RAM for line counting Vertical position registers 1, 2 Port P5 direction register CRT port control register CRT control register Color registers 0 to 3 VSYNC flag Border selection register CRT clock selection register Line counter : CV1, CV2 : P5D : CRTP : CC : CO0 to CO3 : F_VSYNC : MD : CK : Initialization ←“0” ←“000000002” ←“000000002” ←“000000002” ←“000010002” (red) ←“000000102” (blue) ←“000011102” (white) ←“000001102” (cyan) CRTE (bit4 at address 00FE 16) CC (address 00EA 16) P5D (address 00CB 16) CRTP (address 00EC 16) CO0 (address 00E6 16) CO1 (address 00E7 16) CO2 (address 00E8 16) CO3 (address 00E9 16) Block 2 display RAM ← Display character (blank) of block 2 (addresses 0620 16 to 063716) Character color (no output) of block 2 (addresses 06A0 16 to 06B716) CV1 (address 00E1 16) ← Vertical display start position of the 11th line (block 1) ←“0” ←“1” Bit 4 of interrupt control register 1 <CRT interrupt enable bit> Bit 4 of interrupt request register 1 <CRT interrupt request bit> Character size register Horizontal position register CRTE : CRTR : CS : HR : Note: This routine is not interrupt processing routine. |
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