7220 datasheet(177/303 Pages) RENESAS

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APPLICATION

5.1 Example of multi-line display

7220 Group User’s Manual

5-4

(2)

VSYNC interrupt processing routine

The VSYNC interrupt processing routine consists of; multi-line display start processing and multi-line

display correction processing. The correction processing corrects erroneous multi-line display due to

various influences.

Fig. 5.1.4 Flowchart of VSYNC interrupt processing routine

VSYNC interrupt processing routine

CC :

Line counter :

F_VSYNC :

CV1,CV2 :

V_ICON1, V_ICON2 :

A :

X :

Y :

T :

D :

CRT control register

Counter RAM for line counting

VSYNC flag

Vertical position registers 1, 2

Back up RAM for interrupt control

registers 1, 2 during V SYNC interrupt

Accumulator

Index register X

Index register Y

X modified operation mode flag

Decimal operation mode flag

←“0”

←ICON1

←ICON2

←“000000012”

←“000000002”

←“0”

V_ICON1

V_ICON2

ICON1 (address 00FE 16)

ICON2 (address 00FF 16)

Push registers X, Y, A

F_VSYNC

CRTR (bit 4 at address 00FE 16)

CRTE (bit 4 at address 00FC 16)

CC (address 00EA16)

F_VSYNC

←Enable CRT interrupt

←All blocks display on

RETURN

Setting for

multiple

interrupts

Pass this

process only

once at

display start.

←“0”

←“1”

←“0716”

Line counter

←“2”

CV1

←Vertical display start position of the 1st line (block 1)

CV2

←Vertical display start position of the 2nd line (block 2)

CRTR (bit 4 at address 00FE 16)

←“0”

Pop registers X, Y, A

ICON1

ICON2

←“1”

←V_ICON1

←V_ICON2

Setting for

multiple

interrupts

←Push ICON1 contents during V SYNC interrupt

←Push ICON2 contents during V SYNC interrupt

←Enable only Timer 1 interrupt

←Enable multipule interrupt set by steps ,

(Refer to “5.1.7 (2)”)

←Disable all interrupts

Note: The multiple interrupt priority of this system

SYNC

> CRT

Correction for

erroneous

multi-line display

(Refer to “5.1.6”)

←Pop ICON 1 and 2 contents during

SYNC

interrupt (Refer to “5.1.7 (2)”)

ICON1, ICON2:

CRTE :

CRTR :

Interrupt control registers 1, 2

Bit 4 of interrupt control register 1

Bit 4 of interrupt request register 1

interrupt is as below.

Timer 1 > V

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