7220 datasheet(267/303 Pages) RENESAS

267 / 303 page

APPENDIX

6.7 Control registers

7220 Group User’s Manual

6-48

Fig. 6.7.27 CPU mode register

b7 b6 b5 b4 b3 b2 b1 b0

CPU mode register (CPUM) (CM) [Address 00FB16]

After reset

CPU Mode Register

0, 1

Name

Functions

Fix these bits to “0.”

Fix these bits to “1.”

Stack page selection

bit (CM2)

0: 0 page

1: 1 page

6, 7

Indeterminate

Note: This bit is set to “1” after reset release.

Address 00FB16

Fig. 6.7.28 Interrupt request register 1

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register 1 (IREQ1) [Address 00FC

Name

Functions

After reset RW

Interrupt Request Register 1

0 : No interrupt request issued

1 : Interrupt request issued

Timer 1 interrupt

request bit

(TM1R)

Timer 2 interrupt

request bit

(TM2R)

Timer 3 interrupt

request bit

(TM3R)

Timer 4 interrupt

request bit

(TM4R)

CRT interrupt

request bit

(CRTR)

5VSYNC interrupt

request bit

(VSCR)

Multi-master I2C-BUS interface

interrupt request bit

(IICR)

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

0 : No interrupt request issued

1 : Interrupt request issued

V: “0” can be set by software, but “1” cannot be set.

INT3 interrupt

request bit

(IT3R)

0 : No interrupt request issued

1 : Interrupt request issued

]

Note : M37220M3-XXXSP/FP

(See note)

Nothing is assigned. This bit is a write disable bit.

When this bit is read out, the value is “0.”

—

Address 00FC16

(Note)

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