HD6413005F datasheet(9/497 Pages) RENESAS

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5.2.4

IRQ Enable Register (IER) ............................................................................. 80

5.2.5

IRQ Sense Control Register (ISCR) ............................................................... 81

5.3

Interrupt Sources............................................................................................................. 82

5.3.1

External Interrupts .......................................................................................... 82

5.3.2

Internal Interrupts ........................................................................................... 83

5.3.3

Interrupt Vector Table ..................................................................................... 83

5.4

Interrupt Operation ......................................................................................................... 86

5.4.1

Interrupt Handling Process ............................................................................. 86

5.4.2

Interrupt Sequence .......................................................................................... 91

5.4.3

Interrupt Response Time................................................................................. 92

5.5

Usage Notes .................................................................................................................... 93

5.5.1

Contention between Interrupt and Interrupt-Disabling Instruction ................ 93

5.5.2

Instructions that Inhibit Interrupts .................................................................. 94

5.5.3

Interrupts during EEPMOV Instruction Execution......................................... 94

Section 6

Bus Controller............................................................................................ 95

6.1

Overview ........................................................................................................................ 95

6.1.1

Features........................................................................................................... 95

6.1.2

Block Diagram................................................................................................ 96

6.1.3

Input/Output Pins............................................................................................ 97

6.1.4

6.2

Register Descriptions...................................................................................................... 98

6.2.1

Wait Control Register (WCR)......................................................................... 98

6.2.2

Access State Control Register (ASTCR) ........................................................ 99

6.2.3

Wait State Controller Enable Register (WCER)............................................. 100

6.3

Operation ........................................................................................................................ 101

6.3.1

Area Division.................................................................................................. 101

6.3.2

Bus Control Signal Timing ............................................................................. 103

6.3.3

Wait Modes ..................................................................................................... 105

6.3.4

Interconnections with Memory (Example) ..................................................... 111

6.4

Usage Notes .................................................................................................................... 112

6.4.1

Section 7

I/O Ports....................................................................................................... 113

7.1

Overview ........................................................................................................................ 113

7.2

Port 6

........................................................................................................................ 115

7.2.1

Overview......................................................................................................... 115

7.2.2

7.2.3

Pin Functions .................................................................................................. 117

7.3

Port 7

........................................................................................................................ 118

7.3.1

Overview......................................................................................................... 118

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