H83069RF datasheet(197/1003 Pages) RENESAS

197 / 1003 page

Rev. 5.0, 09/04, page 175 of 978

• Figure 6.33 shows typical interconnections when using two 4-Mbit DRAMs, and the

corresponding address map. The DRAMs used in this example are of the 9-bit row address

9-bit column address type. In this example, upper address decoding allows multiple DRAMs

to be connected to a single area. The

RFSH pin is used in this case, since both DRAMs must

be refreshed simultaneously. However, note that RAS down mode cannot be used in this

interconnection example.

CS2 (RAS2)

RD (WE)

A9-A1

D15-D0

A8-A0

D15-D0

PB4 (UCAS)

PB5 (LCAS)

RAS

UCAS

LCAS

A8-A0

D15-D0

RAS

UCAS

LCAS

No.1

No.2

DRAM (No.1)

H'400000

H'47FFFE

H'480000

H'4FFFFE

H'500000

H'5FFFFE

DRAM (No.2)

Not used

(a) Interconnections (example)

CS2 (RAS2)

PB4

(UCAS)

PB5

(LCAS)

Area 2

16-Mbyte mode

(b) Address map

H8/3069R

2-CAS 4-Mbit DRAM

9-bit row address x 9-bit column address

x16-bit organization

RFSH

A19

Figure 6.33 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with

×××× 16-Bit

Organization

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