H83069RF datasheet(201/1003 Pages) RENESAS

201 / 1003 page

Rev. 5.0, 09/04, page 179 of 978

6.6

Interval Timer

6.6.1

Operation

When DRAM is not connected to the H8/3069R chip, the refresh timer can be used as an interval

timer by clearing bits DRAS2 to DRAS0 in DRCRA to 0. After setting RTCOR, selection a clock

source with bits CKS2 to CKS0 in RTMCSR, and set the CMIE bit to 1.

Timing of Setting of Compare Match Flag and Clearing by Compare Match: The CMF flag

in RTMCSR is set to 1 by a compare match output when the RTCOR and RTCNT values match.

The compare match signal is generated in the last state in which the values match (when RTCNT

is updated from the matching value to a new value). Accordingly, when RTCNT and RTCOR

match, the compare match signal is not generated until the next counter clock pulse. Figure 6.38

shows the timing.

H'00

RTCNT

CMF flag

RTCOR

Compare match

signal

Figure 6.38 Timing of CMF Flag Setting

Operation in Power-Down State: The interval timer operates in sleep mode. It does not operate

in hardware standby mode. In software standby mode, RTCNT and RTMCSR bits 7 and 6 are

initialized, but RTMCSR bits 5 to 3 and RTCOR retain their settings prior to the transition to

software standby mode.

Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the

3 state of an RTCNT write cycle, clearing of the counter takes priority and the write is not

performed. See figure 6.39.

H83069RF Datasheet(PDF) 201 Page - Renesas Technology Corp