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TVP70025IPZP Datasheet(PDF) 32 Page - Texas Instruments |
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TVP70025IPZP Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 55 page ![]() Sync Separator Threshold H-PLL Pre-Coast H-PLL Post-Coast TVP70025I SLES232 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com Subaddress 11h Default (20h) 7 6 5 4 3 2 1 0 Sync Separator Threshold [7:0] Sync Separator Threshold [7:0]: Sets how many internal clock reference periods the sync separator counts to before toggling high or low. Sync Separator Threshold [7:0] × (minimum clock period) must be greater than the width of the negative sync pulse. This setting also can affect the position of the VSOUT (see register 22h). NOTE: The internal clock reference is typically 6.5 MHz, but a minimum clock period of 133 ns is recommended to allow for clock variation. 40h = Recommended setting for support of most standard formats. Subaddress 12h Default (00h) 7 6 5 4 3 2 1 0 Pre-Coast [7:0] Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC leading edge. A minimum setting of 1 is required to ensure generation of an internal coast signal. 00h = Minimum setting (default) 01h = 1 HSYNC period (recommendation) FFh = Maximum setting Subaddress 13h Default (00h) 7 6 5 4 3 2 1 0 Post-Coast [7:0] Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC trailing edge. Table 10. Recommended H-PLL Pre-Coast and H-PLL Post-Coast Settings STANDARD H-PLL PRE_COAST H-PLL POST-COAST 480i/p with Macrovision 3 03h 576i/p with Macrovision 3 03h 720p 1 0 1080i 1 0 PC Graphics with SOG 1 0 32 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TVP70025I |
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