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TVP70025IPZP Datasheet(PDF) 9 Page - Texas Instruments |
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TVP70025IPZP Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 55 page  ELECTRICAL CHARACTERISTICS TVP70025I www.ti.com ...................................................................................................................................................................................................... SLES232 – JUNE 2008 IOVDD = 3.3 V, DVDD = 1.8 V, PLL_AVDD = 1.8 V, AVDD = 1.8 V, A33VDD = 3.3 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Interface Input voltage range By design 0.5 1 2 Vpp ZI Input impedance, analog video inputs By design 500 k Ω Digital Logic Interface CI Input capacitance By design 10 pF ZI Input impedance By design 500 k Ω VOH Output voltage high IOH = 2 mA 0.8 IOVDD V VOL Output voltage low IOL = –2 mA 0.2 IOVDD V VOH_SCLK DATACLK output voltage high IOH = 4 mA 0.8 IOVDD V VOL_SCLK DATACLK output voltage low IOH = –2 mA 0.2 IOVDD V VIH High-level input voltage By design 0.7 IOVDD V VIL Low-level input voltage By design 0.3 IOVDD V A/D CONVERTERS ADC full-scale input range Clamp disabled 0.95 1 1.05 Vpp ADC resolution 10-bit range 10 bits DNL DC differential nonlinearity 10 bit, 90 MHz –1 ±0.5 +1 LSB INL DC integral nonlinearity 10 bit, 90 MHz –4 ±1 +4 LSB Missing code 10 bit, 90 MHz none SNR Signal-to-noise ratio 10 MHz, 1 VPP at 90 MSPS 55 dB By design (W/O LPF) BW select Analog 3-dB bandwidth 350 500 MHz [3:0] = 0h Horizontal PLL Phase adjustment 11.6 degree VCO frequency range 9 90 MHz Analog ADC Channel Coarse gain full-scale control range Gain control value NG = 15 ±6 dB Coarse offset full-scale control range Referred to 10-bit ADC output ±124 counts Coarse offset step size Referred to 10-bit ADC output 4 counts Sync Processing Internal clock reference frequency 5 6.5 7 MHz Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TVP70025I |
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