AD7699 datasheet(25/28 Pages) AD

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AD7699

Rev. 0 | Page 25 of 28

READ/WRITE SPANNING CONVERSION WITH A

BUSY INDICATOR

This mode is used when the AD7699 is connected to any host

using an SPI, serial port, or FPGA with an interrupt input. The

connection diagram is shown in Figure 39, and the corresponding

timing is given in Figure 40. For SPI, the host should use CPHA

= CPOL = 1. Reading/writing spanning conversion is shown,

which covers all three modes detailed in the Digital Interface

section.

A rising edge on CNV initiates a conversion, forces SDO to

high impedance, and ignores data present on DIN. After a

conversion is initiated, it continues until completion irrespec-

tive of the state of CNV. CNV must be returned low before the

safe data transfer time, tDATA, and then held low beyond the

conversion time, tCONV, to generate the busy signal indicator.

When the conversion is complete, SDO transitions from high

impedance to low with a pull-up to VIO, which can be used to

interrupt the host to begin data transfer.

After the conversion is complete, the AD7699 enters the

acquisition phase and power-down. The host must enable the

MSB of CFG at this time (if necessary) to begin the CFG

update. While CNV is low, both a CFG update and a data

readback take place. The first 14 SCK rising edges are used to

update the CFG register, and the first 16 SCK falling edges clock

out the conversion results starting with the MSB. The restriction

for both configuring and reading is that they both occur before

the tDATA time elapses for the next conversion. All 14 bits of

CFG[13:0] must be written or they are ignored. Also, if the 16-bit

conversion result is not read back before tDATA elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising

edge can be used to capture the data, a digital host using the

SCK falling edge allows a faster reading rate, provided it has an

acceptable hold time. After the optional 17th SCK falling edge,

SDO returns to high impedance. Note that, if the optional SCK

falling edge is not used, the busy feature cannot be detected if

the LSB for the conversion is low.

If CFG readback is enabled, the CFG register associated with

the conversion result (n − 1) is read back MSB first following

the LSB of the conversion result. A total of 31 SCK falling edges

is required to return SDO to high impedance if this is enabled.

AD7699

MISO

MOSI

SCK

SDO

VIO

FOR SPI USE CPHA = 1, CPOL = 1.

SCK

CNV

DIN

DIGITAL HOST

IRQ

Figure 39. Connection Diagram for the AD7699 with a Busy Indicator

SCK

ACQUISITION (n)

ACQUISITION

(n + 1)

CNV

DIN

SDO

MSB

– 1

BEGIN DATA (n – 1)

BEIGN CFG (n + 1)

CFG

MSB

LSB

+ 1

LSB

SEE NOTE

NOTES

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.

16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.

17/

CONVERSION (n)

CONVERSION

(n – 1)

(QUIET

TIME)

END DATA (n – 2)

END DATA (n – 1)

END CFG (n + 1)

END CFG (n)

DATA

UPDATE (n + 1)

CFG/SDO

LSB

+ 1

LSB

CONVERSION (n – 1)

(QUIET

TIME)

UPDATE (n)

CFG/SDO

CYC

ACQ

HDIN

HSDO

DSDO

SDIN

DATA

CONV

CNVH

DIS

CFG

MSB –1

SCK

SCKH

SCKL

Figure 40. Serial Interface Timing for the AD7699 with a Busy Indicator

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