ADV3202/ADV3203

Rev. 0 | Page 14 of 20

THEORY OF OPERATION

The ADV3202/ADV3203 are single-ended crosspoint arrays

with 16 outputs, each of which can be connected to any one

of 32 inputs.The 32 switchable input stages are connected to

each output buffer to form 32-to-1 multiplexers. There are 16 of

these multiplexers, each with its inputs wired in parallel, for a

total array of 512 stages forming a multicast-capable crosspoint

switch. In addition to connecting to any of the nominal inputs

(INxx), each output can also be connected to an associated OSD

input through an additional 2-to-1 multiplexer at each output.

This 2-to-1 multiplexer switches between the output of the 32-

to-1 multiplexer and the OSD input.

Each input to the ADV3202/ADV3203 is buffered by a receiver.

The purpose of this receiver is to provide overvoltage protection

for the input stages by limiting signal swing. In the ADV3202,

the output of the receiver is limited to ±1.2 V about VREF,

while in the ADV3203, the signal swing is limited to ±1.2 V

about midsupply. This receiver is configured as a voltage

feedback unity-gain amplifier. Excess loop gain bandwidth

product reduces the effect of the closed-loop gain on the

bandwidth of the device. In addition to a receiver, each input

also has a sync-tip clamp for use in ac-coupled applications.

serial data bit. When enabled, the clamp forces the lowest video

voltage to the voltage on the VCLAMP pin. The VCLAMP pin

is common for the entire chip and needs to be driven with a low

impedance to avoid crosstalk.

x1

OUT00

VPOS

VNEG

FROM INPUT

STAGES

VPOS

VNEG

OSD00

OSDS00

Figure 19. Conceptual Diagram of Single Output Channel, G = +1 (ADV3202)

Decoding logic for each output selects one (or none) of the

input stages to drive the output stage. The enabled input stage

drives the output stage, which is configured as a unity-gain

amplifier in the ADV3202 (see Figure 19). In the ADV3203, an

internal resistive feedback network and reference buffer provide

for a total output stage gain of +2 (see Figure 20). The input

voltage to the reference buffer is the VREF pin. This voltage is

common for the entire chip and needs to be driven with a low

impedance to avoid crosstalk.

OUT00

x1

VPOS

VNEG

FROM INPUT

STAGES

VPOS

VNEG

VREF

VPOS

VNEG

OSD00

OSDS00

2kΩ

2kΩ

Figure 20. Conceptual Diagram of Single Output Channel, G = +2 (ADV3203)

IN00

VPOS

VPOS

VNEG

VCLAMP

5µA

TO INPUT

RECEIVER

OFF-CHIP

CAPACITOR

Figure 21. Conceptual Diagram of Sync-Tip Clamp in an

AC-Coupled Application

The output stage of the ADV3202/ADV3203 is designed for low

differential gain and phase error when driving composite video

signals. It also provides slew current for fast pulse response

when driving component video signals.

The outputs of the ADV3202/ADV3203 can be disabled to

minimize on-chip power dissipation. When disabled, a series of

internal amplifiers drive internal nodes such that a wideband

high impedance is presented at the disabled output, even while

the output bus is under large signal swings. (In the ADV3203,

there is 4 kΩ of resistance terminated to the VREF voltage by

the reference buffer). This high impedance allows multiple ICs

to be bussed together without additional buffering. Care must

be taken to reduce output capacitance, which results in more

overshoot and frequency domain peaking. In addition, when

the outputs are disabled and driven externally, the voltage

applied to them should not exceed the valid output swing range

for the ADV3202/ADV3203 to keep these internal amplifiers in

their linear range of operation. Applying excess voltage to the

disabled outputs can cause damage to the ADV3202/ADV3203

and should be avoided (see the Absolute Maximum Ratings

section for guidelines).