TS68230CP8 datasheet(31/61 Pages) STMICROELECTRONICS

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Table 3.3 : Mode 2 Port A Data Paths.

Read Port A Data Register

Write Port A Data Register

Mode

DDR = 0

DDR = 1

DDR = 0

DDR = 1

FOL

FOL, S. B.

Abbreviations :

S. B. - Single Buffered

FOL - Final Output Latch

DDR - Data Direction Register

3.5.2. PORT B - DOUBLE-BUFFERED BIDIREC-

TIONAL DATA. The output buffers of port B are con-

trolled by the level of H1. When H1 is negated, the

port B output buffers (all eight) are enabled and the

pins drive the bidirectional bus. Generally, H1 is ne-

gated by the peripheral in response to an asserted

H2, which indicates that new output data is present

in the double-buffered latches. Following accep-

tance of the data, the peripheral asserts H1, disa-

bling the port B output buffers. Other than controlling

the output buffers, H1 is edge-sensitive as in other

modes.

3.5.2.1. Double-Buffered Input Transfers.

Port B input data that meets the port setup and hold

times is latched on the asserted edge of H3 and pla-

ced in the initial input latch or the final input latch. H3

is edge-sensitive, and may assume any duty-cycle as

long as both high and low minimum times are obser-

ved. The PI/T contains a port status register whose

H3S status bit is set anytime any input data that has

not been read by the bus master is present in the dou-

ble-buffered latches. The action of H4 is programma-

ble and can be programmed as :

1. H4 may be an output pin in the interlocked in-

put handshake protocol. It is asserted when

the port input latches are ready to accept new

data. It is negated asynchronously following

the asserted edge of the H3 input. As soon as

the input latches become ready, H4 is again

asserted. When the input double-buffered

latches are full, H4 remains negated until data

is removed. Thus, anytime the H4 output is as-

serted, new input data may be entered by as-

serting H3. At other times transitions on H3 are

ignored. The H4S status bit is always clear.

When H34 enable in the port general control

2. H4 may be an output pin in the pulsed input

handshake protocol. It is asserted exactly as in

the interlocked input protocol above, but never

remains asserted longer than four clock cy-

cles. Typically, a four clock cycle pulse is ge-

nerated. But in the case that a subsequent H3

asserted edge occurs before termination of the

pulse, H4 is negated asynchronously. Thus,

anytime after the leading edge of the H4 pulse,

new data may be entered in the double-buffe-

red input latches. The H4S status bit is always

clear. When H34 enable is clear, H4 is held ne-

gated.

3.5.2.2. Double-Buffered Output Transfers.

Data, written by the bus master to the PI/T, is stored

in the port’s output latch. The peripheral accepts the

data by asserting H1, which causes the next data to

be moved to the port’s output latch as soon as it is

available. The H1S status bit, in the port status re-

gister, may be programmed for two interpretations.

Normally the status bit is a one when there is at least

one latch in the double-buffered data path that can

accept new data. After writing one byte of data to the

ports, an interrupt service routine could check this bit

to determine if it could store another byte ; thus filling

both latches. When the bus master is finished, it is

often useful to be able to check whether all of the da-

ta has been transferred to the peripheral.The H1S

status control bit of the port A control register pro-

vides this flexibility. The H1S status bit is set when

both output latches are empty. The programmable

options for H2 are :

1. H2 may be an output pin in the interlocked out-

put handshake protocol. It is asserted when

the port output latches are ready to transfer

new data. It is negated asynchronously follo-

wing the asserted edge of the H1 input. As

soon as the output latches become ready, H2

is again asserted. When the output double-

buffered latches are full, H2 remains asserted

until data is removed. Thus, anytime the H2

output is asserted, new output data may be

transferred by asserting H1. At other times

transitions on H1 are ignored. The H2S status

bit is always clear. When H12 enable in the

port general control register is clear, H2 is held

negated.

2. H2 may be an output pin in the pulsed output

handshake protocol. It is asserted exactly as in

the interlocked output protocol above, but ne-

ver remains asserted longer than four clock cy-

TS68230

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