TS68230CP8 datasheet(50/61 Pages) STMICROELECTRONICS

50 / 61 page

6.6. AC ELECTRICAL SPECIFICATIONS

(VCC = 5.0Vdc ± 5%, VSS = 0Vdc, TA =TL to TH unless otherwise specified)

Read and Write Cycle Timings (figures 6.2 and 6.3)

8MHz

10MHz

Number

Parameter

Min.

Max.

Min.

Max.

Unit

1R/W, RS1-RS5 Valid to CS Low (setup time)

(1 )

CS Low to R/W and RS1-RS5 Invalid (hold time)

100

(2 )

CS Low to CLK Low (setup time)

(3 )

CS Low to Data Out Valid

RS1-RS5 Valid to Data Out Valid

140

100

CLK Low to DTACK Low (read/write cycle)

(4 )

DTACK Low to CS High (hold time)

8CS or PIACK or TIACK High to Data Out Invalid (hold time)

9CS or PIACK or TIACK High to D0-D7 High Impedance

CS or PIACK or TIACK High to DTACK High

CS or PIACK or TIACK High to DTACK High Impedance

100

Data In Valid to CS Low (setup time)

CS Low to Data in Invalid (hold time)

100

CLK low on which DMAREQ is asserted to CLK low on

which DMAREQ is negated

2.5

CLK Per

Read Data Valid to DTACK Low (setup time)

(5 )

Synchronized CS to CLK low on which DMAREQ is asserted

3333

CLK Per

CLK Low to DMAREQ Low (delay time)

120

100

CLK Low to DMAREQ High (delay time)

120

100

(5 )

Synchronized H1(H3) to CLK low on which PIRQ is asserted

3333

CLK Per

(5 )

Synchronized CS to CLK low on which PIRQ is high impedance

3333

CLK Per

CLK Low to PIRQ Low or High Impedance

250

225

(6 )

TIN Frequency (external clock) - Prescaler used.

0101

fclk

(Hz)

(7 )

TIN Frequency (external clock) - Prescaler not used.

1/8

fclk

(Hz)

(7 )

TIN Pulse Width High or Low (external clock)

TIN Pulse Width Low (run/halt control)

CLK Per

CLK Low to TOUT High, Low, or High Impedance

250

225

CS, PIACK, or TIACK High to CS, PIACK, or TIACK Low

by solving equations (1) and (2) iteratively for any value of TA.

Notes : 1. See 1.4. Bus Interface Operation for exception.

2. This specification only applies if the PI/T had completed all operations initiated by the previous bus cycle when CS

was asserted. Following a normal read or write bus cycle, all operations are complete within three clocks after the

falling edge of the CLK pin on which DTACK was asserted. If CS is asserted prior to completion of these opera-

tions, the new bus cycle, and hence, DTACK is

postponed.

If all operations of the previous bus cycle were complete when CS was asserted, this specification is made only to

insure that DTACK is asserted with respect to the falling edge of the CLK pin as shown in the timing diagram, not

to guarantee operation of the part. If the CS setup time is violated, DTACK may be asserted as shown, or may be

asserted one clock cycle later.

3. Assuming the RS1-RS5 to data valid time has also expired.

4. This specification imposes a lower bound on CS low time, guaranteeing that CS will be low for at least 1 CLK pe-

riod.

5. Synchronized means that the input signal has seen seen by the PI/T on the appropriate edge of the clock (rising

edge for H1(H3) and falling edge for CS). (Refer to the 1.4. Bus Interface Operation for the exception concerning

CS).

6. This limit applies to the frequency of the signal at TIN compared to the frequency of the CLK signal during each

clock cycle. If any period of the waveform at TIN is smaller than the period of the CLK signal at that instant, then

it is likely that the timer circuit will completely ignore one cycle of the TIN signal.

If these two signals are derived from different sources they will have different instantaneous frequency variations. In

this case the frequency applied to the TIN pin must be distinctly less than the frequency at the CLK pin to avoid lost

cycles of the TIN signal. With signals derived from different crystal oscillators applied to the TIN and CLK pins with

TS68230

50/61

TS68230CP8 Datasheet(PDF) 50 Page - STMicroelectronics

TS68230CP8 Datasheet(HTML) 50 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL