8

6134AS–CASIC–08-Mar-05

ATC13 Summary

7.

Compiled CMOS Memories

The Atmel CMOS Memory Compiler Library enables users to compile memories for the

functions Single-port Synchronous RAM, Dual-port Synchronous RAM, Via Programma-

ble Ultra-low-power (ULP) ROM and Two-port Synchronous Register File according to

their precise requirements. Memories compiled in this way can be instanced as often as

required in designs, alongside cells from other Atmel CBIC libraries.

7.1

Single-port Synchronous SRAM

Key features of the single-port synchronous SRAM are:

• High-density (HD) SRAM

• 400 MHz worst-case cycle time for 4 Kwords x 32 bits

• Zero quiescent current

• 3-state outputs

• Several aspect ratios for optimization of performance

• Separate data-in, data-out pins support a write-through feature

• Asynchronous write-through for testing interface shadow logic

•BIST interface

• Optional sub-word write capability

The single-port SRAM compiler is a high-density high-speed RAM compiler with quies-

cent current consumption equal to zero when the SRAM is not in a read or write mode.

The compiler is optimized for a power supply voltage range of 1.1V to 1.32V and can

operate at voltages as low as 0.9V. The SRAM instances can be built with several

aspect ratios for maximum area and performance optimization. Separate output (Q) and

input (D) pins allow a write-through cycle feature. An asynchronous write through mode

(AWT) allows testing of interface shadow logic. Built-in self-test (BIST) interface allows

for easy connection to most memBIST solutions. The special test modes allow exter-

nally bypassing read and write self-timed circuits and adjusting read and write margins.

The SRAM memory also includes a bit-write feature where selective write to each I/O

can be done. A maskable write enable signal is provided for each I/O for maximum

flexibility.

Table 7-1 gives the range of permitted single-port synchronous RAM configurations.

Note:

1. CM = 4, 8, 16: Column Mux option

Table 7-1.

Configuration Range

Parameter

Min

Max

Increment

Address Locations (words)

16

16K

Word Size (Number of I/O bits)

2

256

1 bit

Total Bits in Core (Word Size x Address Locations)

32

512K