CS4361 datasheet(13/24 Pages) CIRRUS

13 / 24 page

CS4361

Confidential Draft

2/12/08

LR C K

SC L K

Left C h a n n e l

R igh t C h ann e l

SD A T A

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LSB

+5 +4

MSB -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

I²S, 16-Bit data and INT SCLK = 32 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

I²S, Up to 24-Bit data and INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

I²S, Up to 24-Bit data and INT SCLK = 72 Fs if

MCLK/LRCK = 1152

I²S, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

Figure 7. CS4361 Data Format (I²S)

LR C K

SC L K

Left C h a n n e l

R igh t C h ann e l

SD A T A

+3 +2 +1 LS B

+5 +4

MSB -1 -2 -3 -4 -5

+3 +2 +1 LS B

+5 +4

MS B -1 -2 -3 -4

Internal SCLK Mode

External SCLK Mode

Left-Justified, up to 24-Bit Data

INT SCLK = 64 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

INT SCLK = 72 Fs if

MCLK/LRCK = 1152

Left-Justified, up to 24-Bit Data

Data Valid on Rising Edge of SCLK

Figure 8. CS4361 Data Format (Left-Justified)

LR C K

SC L K

Left C h a n n e l

SD A T A

4321

23 22 21 20 19 18

6543

210

23 22 21 20 19 18

32 clocks

R ig h t C h an nel

Internal SCLK Mode

External SCLK Mode

Right-Justified, 24-Bit Data

INT SCLK = 64 Fs if

MCLK/LRCK = 1024, 512, 256, 128, or 64

INT SCLK = 48 Fs if

MCLK/LRCK = 768, 384, 192, or 96

INT SCLK = 72 Fs if

MCLK/LRCK = 1152

Right-Justified, 24-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 48 Cycles per LRCK Period

Figure 9. CS4361 Data Format (Right-Justified 24)

CS4361 Datasheet(PDF) 13 Page - Cirrus Logic

CS4361 Datasheet(HTML) 13 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL