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CS5346 Datasheet(PDF) 18 Page - Cirrus Logic |
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CS5346 Datasheet(HTML) 18 Page - Cirrus Logic |
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18 / 40 page ![]() 18 DS861PP1 CS5346 SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT Inputs: Logic 0 = DGND = AGND = 0 V, Logic 1 = VLC, CL =30pF. 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - µs Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs Clock Low time tlow 4.7 - µs Clock High Time thigh 4.0 - µs Setup Time for Repeated Start Condition tsust 4.7 - µs SDA Hold Time from SCL Falling (Note 17) thdd 0- µs SDA Setup time to SCL Rising tsud 250 - ns Rise Time of SCL and SDA trc, trd -1 µs Fall Time SCL and SDA tfc, tfd - 300 ns Setup Time for Stop Condition tsusp 4.7 - µs Acknowledge Delay from SCL Falling tack 300 1000 ns t bu f t hds t t lo w t hdd t high t su d Sto p S t a r t SD A SCL t irs RS T t hds t t rc t fc t sust t susp St a r t Sto p R epe a t e d t rd t fd t ac k Figure 5. Control Port Timing - I²C Format |
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