CS5346 datasheet(32/40 Pages) CIRRUS

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DS861PP1

CS5346

7.4

MCLK Frequency - Address 05h

7.4.1

Master Clock Dividers (Bits 6:4)

Function:

Sets the frequency of the supplied MCLK signal. See Table 8 for the appropriate settings.

7.5

PGAOut Control - Address 06h

7.5.1

PGAOut Source Select (Bit 6)

Function:

This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to

Table 9.

7.6

Channel B PGA Control - Address 07h

7.6.1

Channel B PGA Gain (Bits 5:0)

Function:

See “Channel A PGA Gain (Bits 5:0)” on page 33.

543

Reserved

MCLK

Freq2

MCLK

Freq1

MCLK

Freq0

Reserved

MCLK Divider

MCLK Freq2

MCLK Freq1

MCLK Freq0

÷1

000

÷1.5

001

÷2

010

÷3

011

÷4

100

Reserved

101

Reserved

Table 8. MCLK Frequency

543

Reserved

PGAOut

Reserved

PGAOut

PGAOutA & PGAOutB

High Impedance

PGA Output

Table 9. PGAOut Source Selection

543

Reserved

Gain5

Gain4

Gain3

Gain2

Gain1

Gain0

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