5

3039K–CNFG–2/08

AT17F040/080

5.

Pin Description

5.1

DATA(1)

Three-state DATA output for configuration. Open-collector bi-directional pin for programming.

5.2

CLK(1)

Clock input. Used to increment the internal address and bit counter for reading and

programming.

5.3

PAGE_EN(2)

Input used to enable page download mode. When PAGE_EN is high the configuration download

address space is partitioned into 4 equal pages. This gives users the ability to easily store and

retrieve multiple configuration bitstreams from a single configuration device. This input works in

conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired.

When SER_EN is Low (ISP mode) this pin has no effect.

Notes:

1. This pin has an internal 20 K

Ω pull-up resistor.

2. This pin has an internal 30 K

Ω pull-down resistor.

Table 5-1.

Pin Description

Name

I/O

AT17F040

AT17F080

8

LAP

20

PLCC

20 PLCC

(Virtex)

8

LAP

20

PLCC

44

TQFP

DATA

I/O

12112

40

CLK

I

24324

43

PAGE_EN

I

–16–

–16

39

PAGESEL0

I

–

11

–

–

11

14

PAGESEL1

I

–7––7

19

RESET/OE

I

36836

13

CE

I

4

8104

815

GND

–

510

11510

18

CEO

O

614

13614

21

A2

I

READY

O

–15

15–15

23

SER_EN

I

7

17

18

7

17

35

V

CC

–

8

20

20

8

20

38