Features

– 450 ps Max NAND2 Propagation Delay at 4.5V, 720 ps at 2.7V and FO = 5

– Min 610 MHz Toggle Frequency at 4.5V, 320 MHz at 2.7V

– 1.96 µW/Gate/MHz at 5V

– 0.6 µW/Gate/MHz at 3V

– I/O with Slew Rate Control

– Internal Decoupling

– Signal Filtering between Periphery and Core

– Application Dependent Supply Routing and Several Independant Supply Sources

Power Management

Description

The MG2RT series is a 0.5 micron, array based, CMOS product family. Several arrays

up to 480K gates cover most system integration needs. The MG2RT is manufactured

using a 0.5 micron drawn, 3 metal layer CMOS process, called SCMOS 3/2RT.

The base cell architecture of the MG2RT series provides high routability of logic with

extremely dense compiled memories: RAM and DPRAM. ROM can be generated

using synthesis tools.

Accurate control of clock distribution can be achieved by PLL hardware and CTS

(Clock Tree Synthesis) software. New noise prevention techniques are applied in the

array and in the periphery: three or more independent supplies, internal decoupling,

customiszation dependent supply routing, noise filtering, skew controlled I/Os, low

swing differential I/Os, all contribute to improve the noise immunity and reduce the

emission level.

The MG2RT is supported by an advanced software environment based on industry

standards linking proprietary and commercial tools. Verilog, Modelsym and Design

Compiler are the reference front-end tools. Floor planning associated with timing-

driven layout provides a short back-end cycle.

Rad Tolerant

350K Used Gates

0.5 µm CMOS

Sea of Gates

MG2RT