4

4115L–AERO–06/05

MG2RT

Power Supply

and Noise

Protection

The speed and density of the SCMOS3/2RT technology cause large switching current spikes for

example when:

•

either 16 high current output buffers switch simultaneously,

•

or 10% of the 480,000 gates are switching within a window of 1 ns.

Sharp edges and high currents cause some parisitic elements in the packaging to become sig-

nificant. In this frequency range, the package inductance and series resistance should be taken

into account. It is known that an inductor slows down the settling time of the current and causes

voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself

or disturb the external application (ground bounce).

In order to improve the noise immunity of the MG core matrix, several mechanisms have been

implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O

buffer switching noise and the other to protect the I/O buffers against the switching noise coming

from the matrix.

I/O Buffers

Switching

Protection

Three features are implemented to limit the noise generated by the switching current:

•

The power supplies of the input and output buffers are separated.

•

The rise and fall times of the output buffers can be controlled by an internal regulator.

•

A design rule concerning the number of buffers connected on the same power supply line

has been imposed.

Matrix Switching

Current Protection

This noise disturbance is caused by a large number of gates switching simultaneously. To allow

this without impacting the functionality of the circuit, three new features have been added:

•

Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop.

•

A power supply network has been implemented in the matrix. This solution reduces the

number of parasitic elements such as inductance and resistance and constitutes an artificial

VDD and Ground plane. One mesh of the network supplies approximately 150 cells.

•

A low pass filter has been added between the matrix and the input to the output buffer. This

limits the transmission of the noise coming from the ground or the VDD supply of the matrix

to the external world via the output buffers.