AT40KAL datasheet(3/38 Pages) ATMEL

3 / 38 page

AT40KAL

4263B–AERO–06/03

dard schematic and synthesis tools to create the fastest, most efficient designs avail-

able.

The patented AT40KAL series architecture employs a symmetrical grid of small yet

powerful cells connected to a flexible busing network. Independently controlled clocks

and resets govern every column of cells. The array is surrounded by programmable I/O.

Devices offer 50,000 usable gates, and have 3,056 registers. AT40KAL series FPGAs

utilize a reliable 0.35µ single-poly, 4-metal CMOS process and are 100% factory-tested.

Atmel’s PC- and workstation-based integrated development system (IDS) is used to cre-

ate AT40KAL series designs. Multiple design entry methods are supported.

The Atmel architecture was developed to provide the highest levels of performance,

functional density and design flexibility in an FPGA. The cells in the Atmel array are

small, efficient and can implement any pair of Boolean functions of (the same) three

inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays

with large numbers of cells, greatly multiplying the functionality in each cell. A simple,

high-speed busing network provides fast, efficient communication over medium and

long distances.

AT40KAL Datasheet(PDF) 3 Page - ATMEL Corporation