ACS8526P datasheet(7/74 Pages) SEMTECH

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ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 4.01/June 2006 © Semtech Corp.

Page 7

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ACS8526 LC/P LITE

Input frequencies supported range from 2 kHz to

155.52 MHz. Common E1, DS1, OC-3 and sub-divisions

are supported as spot frequencies that the DPLLs will

directly lock to. Any input frequency, up to 100 MHz, that

is a multiple of 8 kHz can also be locked to via an inbuilt

programmable divider.

In addition to the SEC inputs, there are four configuration

pins IP_FREQ [2:0] and SONSDHB used to configure the

input to expect a particular input frequency (same value

applies to both inputs), and a control pin SRCSW for

switching between SEC1 and SEC2 as the selected input

reference to which the device tries to lock.

Preconfiguring Inputs - Expected Input Frequency

The inputs SEC1 and SEC2 must be preconfigured to

expect a particular input frequency.

The expected input frequencies can be selected from a

range of spot frequencies by either:

Hardware selection: configuring the hardware pins

IP_FREQ [2:0] and SONSDHB, which are read on reset

cnfg_ref_source_frequency and cnfg_input_mode

registers.

Hardware Selection of Expected I/P Frequency

The combined pin states of IP_FREQ [2:0] and SONSDHB

represent a 4-bit word which addresses a particular

frequency value as given in Table 4.

The frequency selected by the hardware configuration is

always applied to both inputs on Power-up or Reset, so

both will be preconfigured to expect the same frequency.

If SEC1 and SEC2 are required to expect different

frequencies, then these inputs must be subsequently

reconfigured by programming the appropriate registers.

The expected input frequencies can be programmed by

writing to the cnfg_ref_source_frequency registers

(Reg. 22 and 23) and ip_sonsdhb (Bit 2 of

cnfg_input_mode,Reg. 34), via the serial interface. This

must not be done until after the end of the initialization

period (see “Initialization” on page 8).

Note...Any subsequent reset will cause these registers to be

overwritten by values that equate to the single hardware

selected frequency on the pins at the time of reset, i.e both

inputs will be configured to expect the same input frequency.

After a reset and initialization period, any change of state on

IP_FREQ [2:0] or SONSDHB will have no effect on the device

configuration, as these are only read during the reset period.

The register programming approach provides a greater

range of frequencies than the hardware selection

method: more spot frequencies, plus frequencies derived

using DivN Mode up to 100 MHz (TTL technology limit).

Preconfiguring Inputs- SONET/SDH

The cnfg_input_mode register bit ip_sonsdhb is used to

select SDH or SONET mode for the entire device and its

setting affects parameters other than just the expected

input frequency selection, e.g. output frequency. To set

the device for use in a SONET network, set ip_sonsdhb =

1. For SDH, set ip_sonsdhb = 0.

Input Locking Frequency Modes

Each input port has to be configured to receive the

expected input frequency. To achieve this, three input

locking frequency modes are provided: Direct Lock,

Lock8K and DivN.

Direct Lock Mode

In Direct Lock mode, DPLL1 can lock to the selected input

at the spot frequency of the input, for example 19.44 MHz

performs the DPLL phase comparisons at 19.44 MHz.

In Lock8K and DivN modes an internal divider is used

prior to DPLL1 to divide the input frequency before it is

used for phase comparisons.

Table 4 Hardware Configuration for Selecting Expected

Input Frequency on SEC1 and SEC2

IP_FREQ Pins

SONSDHB

Input frequency

210

8 kHz

2.048 MHz

1.544 MHz

6.48 MHz

19.44 MHz

25.92 MHz

38.88 MHz

51.84 MHz

77.76 MHz

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