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ACS8526P Datasheet(PDF) 1 Page - Semtech Corporation |
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ACS8526P Datasheet(HTML) 1 Page - Semtech Corporation |
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1 / 74 page  Revision 4.01/June 2006 © Semtech Corp. Page 1 www.semtech.com ACS8526 LC/P LITE ADVANCED COMMUNICATIONS FINAL Line Card Protection Switch for PDH, SONET or SDH Systems ADVANCED COMMUNICATIONS FINAL DATASHEET The ACS8526 is a highly integrated single-chip solution for protection switching between two SECs (SDH/SONET Equipment Clocks) from Master and Slave SETS clock cards, for line cards in a PDH, SONET or SDH Network Element. The ACS8526 has fast activity monitors on the inputs and will raise a flag on a pin if there is a loss of activity on the currently selected input. The protection switching between the input reference clock sources is controlled by an external pin. The ACS8526 has two SEC reference clock input ports, configured for expected frequency by setting hardware pins or by writing to registers via the serial interface. The ACS8526 can perform frequency translation, converting, for example, an 8 kHz SEC input clock from a backplane into a 155.52 MHz clock for local line cards. The ACS8526 generates two independent SEC clock outputs, one on a PECL/LVDS port and one on a TTL/CMOS port, at spot frequencies configured by hardware pins, or by writing to registers via the serial interface. The hardware selectable spot frequencies range from 1.544 MHz up to 155.52 MHz, with further options for N x E1/DS1 and 311.04 MHz via register selection. The ACS8526 also provides an 8 kHz Frame Sync output and 2 kHz Multi-Frame Sync output, both with programmable pulse width and polarity. Advanced configuration possibilities are available via the serial port (which can be SPI compatible), however the basic configuration of I/O frequencies and SONET/SDH selection by hardware make the device suitable for standalone operation, i.e., no need for a microprocessor. Line card protection switch - partners Semtech SETS devices for Stratum 3E/3/4E/4 PDH, SONET or SDH applications High performance DPLL/APLL solution Output jitter compliant to STM-1 Two independent SEC inputs ports (TTL) Four independent output ports: Two clock ports: one PECL/LVDS, one TTL Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync TTL I/O ports: spot frequencies 2 kHz to 77.76 MHz PECL/LVDS port: spot frequencies 2 kHz to 311 MHz N x E1/DS1 mode Programmable pulse width and polarity on Syncs SONET/SDH frequency translation Digital Holdover mode on input failure Separate activity monitors and register alarms on each input. “Loss of activity” on selected input flagged on dedicated pin Source switch under external hardware control PLL “Locked” and “Acquisition” bandwidth selectable from 18, 35 or 70 Hz Configurable via serial interface or hardware pins Output clock phase continuity to GR-1244-CORE[13] Single 3.3 V operation, 5 V I/O compatible IEEE 1149.1 JTAG Boundary Scan is supported Operating temperature (ambient) of -40 to +85°C Available in LQFP 64 package Lead (Pb)-free version available (ACS8526T), RoHS and WEEE compliant. Figure 1 Block Diagram of the ACS8526 LC/P LITE Block Diagram Description Features IEEE 1149.1 JTAG Chip Clock Generator TCK TDI TMS TRST TDO F8526D_001BLOCKDIA_03 Selector DPLL1 DPLL2 E1/DS1 Synthesis APLL2 APLL3 APLL 1 Output Frequencies/MHz 01 Output: 19.44 25.92 34.368 (E3) 38.88 44.736 (DS3) 51.84 77.76 155.52 2 x SEC TTL inputs SEC Inputs: Programmable Frequencies N x 8 kHz 1.544 MHz 2.048 MHz 6.48 MHz 19.44 MHz 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz FrSync 8 kHz (TTL) Output Port Frequency Selection Priority Table Register Set Digital Feedback SPI Compatible Serial Interface Port TCXO or XO Input SEC Port 01 (LVDS/PECL) 02 (TTL) MFrSync 2 kHz (TTL) SEC Outputs: Sync Outputs: SEC1 SEC2 MUX 2 MUX 1 02 Output: 1.544 2.048 3.088 19.44 25.92 34.368 (E3) 38.88 44.736 (DS3) 51.84 77.76 SRCSW OP_FREQ1 OP_FREQ2 IP_FREQ SONSDHB LOS_ALARM |
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