ACS8526P datasheet(19/74 Pages) SEMTECH

19 / 74 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 4.01/June 2006 © Semtech Corp.

Page 19

www.semtech.com

ACS8526 LC/P LITE

Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default. When High, SONET is default.

Table 8 Output Reference Source Selection Table

Port

Name

Output Port

Technology

Frequencies Supported

Output

LVDS/PECL

(LVDS default)

Frequency selection as per Table 9 and Table 13

Output

TTL/CMOS

FrSync

TTL/CMOS

FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A.

MFrSync

TTL/CMOS

MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A.

Table 9 Output Frequency Selection

Frequency (MHz, unless stated otherwise)

DPLL1 Mode

DPLL2 Mode

APLL2 Input Mux

Jitter Level (typ)

rms

(ps)

p-p (ns)

2 kHz

77.76 MHz Analog

0.6

2 kHz

Any digital feedback

mode

1400

8 kHz

77.76 MHz Analog

0.6

8 kHz

Any digital feedback

mode

1400

1.536

12E1 mode

Select DPLL2

500

2.3

1.536

Select DPLL1 12E1

250

1.5

1.544

16DS1 mode

Select DPLL2

200

1.2

1.544

Select DPLL1 16DS1

150

1.0

1.544

via Digital1 or Digital2 (not Output O1)

77.76 MHz Analog

3800

1.544

via Digital1 or Digital2 (not Output O1)

Any digital feedback

mode

3800

2.048

12E1 mode

Select DPLL2

500

2.3

2.048

Select DPLL1 12E1

250

1.5

2.048

16E1 mode

Select DPLL2

400

2.0

2.048

Select DPLL1 16E1

220

1.2

2.048

(not Output O1)

12E1 mode

900

4.5

2.048

via Digital1 or Digital2 (not Output O1)

77.76 MHz Analog

3800

2.048

via Digital1 or Digital2 (not Output O1)

Any digital feedback

mode

3800

2.059

16DS1 mode

Select DPLL2

200

1.2

2.059

Select DPLL1 16DS1

150

1.0

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