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ATA5425-PLSW Datasheet(PDF) 92 Page - ATMEL Corporation

Part # ATA5425-PLSW
Description  UHF ASK/FSK Transceiver
PDF  100 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATA5425-PLSW Datasheet(HTML) 92 Page - ATMEL Corporation

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4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
13.6
Minimum time period
between edges at pin
SDO_TMDO in RX
transparent mode
XLIM = 0
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
XLIM = 1
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
31
T
DATA_min
10
×
TXDCLK
µs
A
13.7
Edge
-to-edge time
period of the data signal
for full sensitivity in RX
mode
BR_Range_0
BR_Range_1
BR_Range_2
BR_Range_3
T
DATA
200
100
50
25
500
250
125
62.5
µs
B
14
TX Mode
14.1
Start
-up time
From IDLE mode
TStartup
331.5
× T
DCLK
331.5
× T
DCLK
µs
A
15
Configuration of the Transceiver with 4-wire Serial Interface
15.1
CS set
-up time to rising
edge of SCK
33, 35
T
CS_setup
1.5
×
TDCLK
µs
A
15.2
SCK cycle time
33
TCycle
2µs
A
15.3
SDI_TMDI set
-up time
to rising edge of SCK
32, 33
TSetup
250
ns
C
15.4
SDI_TMDI hold time
from rising edge of SCK
32, 33
THold
250
ns
C
15.5
SDO_TMDO enable
time from rising edge of
CS
31, 35
TOut_enable
250
ns
C
15.6
SDO_TMDO output
delay from falling edge
of SCK
CL = 10 pF
31, 35
TOut_delay
250
ns
C
15.7
SDO_TMDO disable
time from falling edge of
CS
31, 33
T
Out_disable
250
ns
C
15.8
CS disable time period
35
T
CS_disable
1.5
×
TDCLK
µs
A
15.9
Time period SCK low to
CS high
33, 35
TSCK_setup1
250
ns
C
15.10
Time period SCK low to
CS low
33, 35
T
SCK_setup2
250
ns
C
15.11
Time period CS low to
SCK high
33, 35
T
SCK_hold
250
ns
C
16. Digital Timing Characteristics (Continued)
All parameters refer to GND and are valid for Tamb =25°C. VVS1 =VS2 = 3.0V (1 Li battery application (3V)), VVS2 = 6.0V (2 Li battery
application (6V)) and VVS2 =5.0V (Base-station Application(5V)) unless otherwise specified.
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter



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