AT90USB646 datasheet(267/459 Pages) ATMEL

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267

7593H–AVR–11/08

ATmega32U6/AT90USB64/128

22. USB Device Operating modes

22.1

Introduction

The USB device controller supports full speed and low speed data transfers. In addition to the

default control endpoint, it provides six other endpoints, which can be configured in control, bulk,

interrupt or isochronous modes:

• Endpoint 0:programmable size FIFO up to 64 bytes, default control endpoint

• Endpoints 1 programmable size FIFO up to 256 bytes in ping-pong mode.

• Endpoints 2 to 6: programmable size FIFO up to 64 bytes in ping-pong mode.

The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to the

minimum.

22.2

Power-on and reset

The next diagram explains the USB device controller main states on power-on:

Figure 22-1. USB device controller states after reset

The reset state of the Device controller is:

• the macro clock is stopped in order to minimize the power consumption (FRZCLK set),

• the USB device controller internal state is reset (all the registers are reset to their default

value. Note that DETACH is set.)

• the endpoint banks are reset

• the D+ or D- pull up are not activated (mode Detach)

The D+ or D- pull-up will be activated as soon as the DETACH bit is cleared and VBUS is

present.

The macro is in the ‘Idle’ state after reset with a minimum power consumption and does not

need to have the PLL activated to enter in this state.

The USB device controller can at any time be reset by clearing USBE (disable USB interface).

22.3

Endpoint reset

An endpoint can be reset at any time by setting in the UERST register the bit corresponding to

the endpoint (EPRSTx). This resets:

• the internal state machine on that endpoint,

• the Rx and Tx banks are cleared and their internal pointers are restored,

Reset

Idle

RESET

USBE=0

<any

other

state>

USBE=0

USBE=1

UID=1

AT90USB646 Datasheet(PDF) 267 Page - ATMEL Corporation

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