AT90USB1286 datasheet(61/459 Pages) ATMEL

61 / 459 page

7593H–AVR–11/08

ATmega32U6/AT90USB64/128

Figure 8-5.

Brown-out Reset During Operation

8.0.6

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT. Refer to

page 63 for details on operation of the Watchdog Timer.

Figure 8-6.

Watchdog Reset During Operation

8.0.7

MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by

the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic

zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

VCC

RESET

TIME-OUT

INTERNAL

RESET

VBOT-

VBOT+

tTOUT

Bit

76543

210

–

JTRF

WDRF

BORF

EXTRF

PORF

MCUSR

Read/Write

RRRR/W

R/W

Initial Value

000See Bit Description

AT90USB1286 Datasheet(PDF) 61 Page - ATMEL Corporation

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