Off-line Phase Timing (Internal RAMs Loading with Charge Mode ”1”)

DC LK

OF L

I0 -I7

EPA 0 -E PA2 +

A0 -A 9

AD D R E S S 0

AD D R E S S 1

AD D R E S S n

MC LK

DATA 0

D ATAn

DATA 1

W .A.R .P. st o re s D ATA0

W .A.R . P. st o re s D ATA1

W .A.R .P. st o re s D ATAn

PR S T

CH M

SYN C

Timing Table Description: OFF-LINE phase (CHM ”1”)

- CHM [INPUT] high will enable the ’automatic downloading’, specifying the address of the non-volatile

memory where are data to be loaded into W.A.R.P.. Internal memory addresses are automatically

generated.

- MCLK [INPUT] must be connected with the external synchronization signal.

- PRST [INPUT] must be set high to enable the device.

- OFL [INPUT] must be set high to enable the loading phase of data into the internal RAMs of W.A.R.P..

- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7) coming from the external database.

SYNC frequency is MCLK/32.

- DCLK [INTERNAL] sets the working frequencyaccordingto the OFL control signal. It drives the addressing

of data coming from the external memory support by the I0-I7 input bus. The external memory support must

return the data (addressed by EPA0-EPA2+A0-A9 [OUTPUT]) into I0-I7 in a period of time no longer than

half a period of DCLK. DCLK frequency is MCLK/32.

Figure 9.

Block Diagram for W.A.R.P. downloading (CHM ”1”)

12/19

W.A.R.P.1.1