On-line Phase Timing (Output Generation) Working Frequency 40MHz

O0-O9

MCLK

NP

EP

end of

computation

OCNT0-3

STB

start of

c om putation

d ata output

st orag e

data output

st orag e

la st output da ta

OUT NUM n -1

la st output number

NEW DATA

ACQUISITION

DATA OUT 1

d ata ou tput

st ora g e

OUT NUM 1

OUT NUM 2

DATA OUT n-1

DATA OUT 2

Timing Table Description: ON-LINE phase

- MCLK [INPUT] must be connectedwith the external synchronization signal.

- OFL [INPUT] must remain low during this phase.

- NP [OUTPUT] remains high during this phase.

- EP [OUTPUT] is set high during this phase.

- STB [OUTPUT] is set high for a clock period every time an output value has been calculated. It informs

that it is possible to utilize the output which is situated in the output bus (O0-O9). The STB pulse starts at

the rising edge of the MCLK and stops at the next rising edge of the MCLK. At the falling edge of the STB

the data situated on the O0-O9 bus can be stored.

- The current output on the O0-O9 [OUTPUT] bus is provided exactly when the STB signal rises and it

does not change until a new STB signal occurs.

- The output identifier on the OCNT0-OCNT3 [OUTPUT] bus is provided exactly when the STB signal rises

and it does not change until a new STB signal occurs.

- NP [OUTPUT] is set low when the penultimate STROBE is disabled allowing a new acquisition phase to

start while W.A.R.P. is still elaborating the last output.

- When the last output has been provided, EP will be automatically set low.

14/19

W.A.R.P.1.1