1469 datasheet(13/20 Pages) LINER

13 / 20 page

LT1469

1469fa

APPLICATIONS INFORMATION

Capacitive Loading

The LT1469 drives capacitive loads of up to 100pF in unity-

gain and 300pF in a gain of –1. When there is a need to

drive a larger capacitive load, a small series resistor should

be inserted between the output and the load. In addition,

a capacitor should be added between the output and the

inverting input as shown in Figure 3.

Settling Time

The LT1469 is a single stage ampliﬁer with an optimal

thermal layout that leads to outstanding settling per-

formance. Measuring settling even at the 12-bit level is

very challenging, and at the 16-bit level requires a great

deal of subtlety and expertise. Fortunately, there are two

excellent Linear Technology reference sources for settling

measurements—Application Notes 47 and 74. Appendix B

of AN47 is a vital primer on 12-bit settling measurements

and AN74 extends the state-of-the-art while concentrating

on settling time with a 16-bit current output DAC input.

The settling of the DAC I-to-V converter on the front page

was measured using the exact methods of AN74. The

optimum nulling of the DAC output capacitance requires

15pF across the 12k feedback resistor. The theoretical limit

for 16-bit settling is 11.1 times this RC time constant or

2μs. The actual settling time is 2.4μs at the output of the

LT1469.

The RC output noise ﬁlter adds a slight settling time delay

but reduces the noise bandwidth to 1.6MHz which increases

the output resolution for 16-bit accuracy.

Figure 3. Driving Capacitive Loads

–

VOUT

RO ≥ (1 + RF/RG)/(2 • CL • 5MHz)

RF ≥ 10RO

CF = (2RO/RF)CL

1/2 LT1469

VIN

1469 F03

1469 Datasheet(PDF) 13 Page - Linear Technology