F75121RG datasheet(9/45 Pages) FINTEK

9 / 45 page

- 7 -

July, 2007

V0.24P

I2C_ADDR

INtsd100k

The GPIO serial bus hardware power on

setting pin. Default address is 0x9C

(when I2C_ADDR=0).

Another one is

0x6E (when I2C_ADDR=1). This pin

internal pull-down 100k to Ground. If this

pin is pull-up 10k to VSB3V, this pin will

be trapped to 1.

SDATA

I/OD12ts

VSB3V

SMbus data.

SCLK

INts

VSB3V

SMBus clock

RSTOUT#

OD12

VSB3V

System reset signal when the Reset-Out

timer is time out. This pin will generate

100mS pulse when the Reset-Out timer

is timeout.

SLOTOCC#

INts

VBAT

24,23,22,21,

20,19

VIDOUT[0:5]

OD16

VSB3V

CPU Voltage ID output.

SEL

INtsd100k

VSB3V

Default pull up to 3VSB.

2,27,26,25

GPIO30,GPIO31,

GPIO32,GPIO33

I/OD12ts

VSB3V

General purpose I/O pins.

6. Functional Description

6.1 General Description

The F75121 provides VIDIN, VIDOUT function. It can latch the VIDIN from CPU side, and output VIDOUT to

PWM. The VIDOUT value can be programmed by the interface GPIO Serial Bus serial interface.

Dedicate GPIO functions. That includes two set watchdog timer. The watchdog timer timeout unit is set to second

and range is 0 to 31 seconds. When the timeout has occurred, that will generate a status bit to indicate it and write

one will be clear.

All GPIO can be programmed to logic one or zero or high pulse or low pulse.

F75121RG Datasheet(PDF) 9 Page - Feature Integration Technology Inc.

F75121RG Datasheet(HTML) 9 Page - Feature Integration Technology Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL