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July, 2007

V0.28P

Providing CPU on board detection (SLOTOCC#). The detection circuit is powered by battery. That is latch circuit

is powered by VBAT. The de-bounce circuit should be added to avoid low power noise. The de-bounce circuit is

generated by internal low frequency clock with 32K Hz to filter out the low-to-high or high-to-low glitch.

6.2 Access Interface

The F75122 provides one serial access interface, Serial Bus, to read/write internal registers. The address of Serial

Bus is configurable by using power-on trapping of standby power VBS3V. The pin 11 (GPIO11/I2C _ADDR) is

multi-function pin. During the VSB 3V power-on, this pin serves as input detection of logic high or logic low. This pin is

default pull-down resistor with 100K ohms mapping the Serial Bus address 0x9C (1001_1100).

Another Serial Bus

address 0x6E (0110_1110) is set when external pull-up resistor with 10K ohms is connected in this pin.

6.3 The SMBus access timing are shown as follow:

0

Start By

Master

01011

01

D7

D6

D5

D4

D3

D2

D1

D0

Ack

by

122R

R/W

Ack

by

122R

SCL

SDA

D7

D6

D5

D4

D3

D2

D1

D0

Stop

by

Master

SCL

SDA (Continued)

78

0

7

8

0

78

Frame 2

Internal Index Register Byte

(Continued)

Frame 3

Data Byte

Frame 1

Serial Bus Address Byte

Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte