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F75122RG Datasheet(PDF) 21 Page - Feature Integration Technology Inc.

Part # F75122RG
Description  Dynamic VID Control 8 GPIO Datasheet
PDF  35 Pages
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Manufacturer  FINTEK [Feature Integration Technology Inc.]
Direct Link  http://www.fintek.com.tw/eng
Logo FINTEK - Feature Integration Technology Inc.

F75122RG Datasheet(HTML) 21 Page - Feature Integration Technology Inc.

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- 19 -
July, 2007
V0.28P
7.39 VID Input Latch Register – Index 33h
Power-on default [7:0] =000x_xxxxb
Bit
Name
R/W
PWR
Description
7-6
Reserved
RO
--
Reserved, read return 0.
5-0
LVIDIN
RO
VSB3V
VIDIN data.
7.40 RSTOUT Control Register – Index 34h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7-3
Reserved
RO
2
SEL_RST_2S
R/W
VSB3V
When set this bit to 1, the RSTOUT low pulse width is 2 Sec, if set to
0 the low pulse width is 100ms.
1
RSTOUT_OINV
R/W
VSB3V
RSTOUT# output level inverting. When write 1, the output pin will be
inverted. Default is low active when time is out.
0
STS_RSTOUT
R/W
VSB3V
Indicate RSTOUT is occurred. Write 1 to clear this bit. Writing 0 is
invalid.
7.41 RSTOUT Control Register – Index 35h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
RST_ENABLE
R/W
VSB3V
Enable RESET Output Timer. If set to 1, the RSTOUT timer will be
started. When RSTOUT# is asserted, low pulse is occurred, the VID
will re-latched and disable EN_VIDOUT. The status of Reset Out is
stored in CR02.b1.
6-0
WD1_PTIME
R/W
VSB3V
RSTOUT Pre-counter time in second.
000_0000b – 0 second (Default)
000_0001b – 1 second
000_0010b – 2 seconds
:
111_1111b – 127 seconds
Reset Out timing is shown as follows.



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