2

Symbol

Parameter

Min

Max

Units

Conditions

I

DD

V

15

mA

V

f

High voltage supply current

-10

µA

(total of all outputs)

100

µA

V

OH

High-level output

Data out

V

V

I

+1

Low-level output

Data out

+0.5

V

I

IH

High-level logic input current

1

Low-level logic input current

-1

HV output source current

-2

mA

see Figures 8a and 8b

-0.1

mA

V

see Figure 8a and 8b

10

%

Electrical Characteristics

Symbol

Parameter

Min

Max

Units

Conditions

f

CLK

Clock frequency

DC

8

MHz

Per register

Clock width high or low

62

ns

t

SU

Data set-up time before clock rises

10

ns

t

H

Data hold time after clock rises

15

ns

500

ns

t

DHL

Delay time clock to data high to low

70

ns

C

t

DLH

Delay time clock to data low to high

70

ns

C

Delay time clock to LE low to high

25

ns

t

WLE

Width of LE pulse

25

ns

t

SLE

LE set-up time before clock rises

0

ns

Maximum allowable clock rise and fall time

100

ns

(10% and 90% points)

Notes 1: Current going out of the chip is considered negative.

HV57009