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HV574 Datasheet(PDF) 2 Page - Supertex, Inc

Part # HV574
Description  100 MHz, 80-Channel Serial To Parallel Converter With Push-Pull Outputs
PDF  5 Pages
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Manufacturer  SUTEX [Supertex, Inc]
Direct Link  http://www.supertex.com
Logo SUTEX - Supertex, Inc

HV574 Datasheet(HTML) 2 Page - Supertex, Inc

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HV574
Electrical Characteristics (over recommended commercial operating conditions unless noted)
DC Characteristics
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD supply current
30
mA
V
DD = VDD max
fCLK = 25MHz
I
PP
Quiescent V
PP supply current
100
µA
Outputs high
100
µA
Outputs low
I
DDQ
Quiescent V
DD supply current
100
µA
All V
IN = VDD
V
OH
High-level output
HV
OUT
V
PP - 9V
V
I
O= -30mA, VPP = 80V
Data out
VDD - 0.5
V
IO= -100µA
V
OL
Low-level output
HV
OUT
3.75
V
I
O = 15mA, VDD = 5V
Data out
0.5
V
I
O= 100µA
IIH
High-level logic input current
1.0
µAVIH = VDD
I
IL
Low-level logic input current
-1.0
µAVIL = 0V
AC Characteristics (T
A = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points])
Symbol
Parameter
Min
Max
Units
Conditions
fCLK
Clock frequency
0.001
25
MHz
VDD = 4.5V, TJ = 25°C
0.001
20
V
DD = 4.5V, TJ = 125°C
t
WL,tWH
Clock width high or low
20
ns
tSU
Data set-up time before clock rises
0
ns
t
H
Data hold time after clock rises
15
ns
tON, tOFF
Time from latch enable to HVOUT
500
ns
CL = 15pF
tDHL
Delay time clock to data high to low
38
ns
CL = 15pF, VDD = 5.0V
t
DLH
Delay time clock to data low to high
38
ns
C
L = 15pF, VDD = 5.0V
tDLE*
Delay time clock to LE low to high
25
ns
tWLE
Width of LE pulse
25
ns
t
SLE
LE set-up time before clock rises
0
ns
tr, tf
Output rise/fall time
1.0
µsCL = 600pF,
HV
OUT from 0 to 60V
* t
DLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR output to stabilize).
Symbol
Parameter
Min
Max
Units
V
DD
Logic supply voltage
4.5
5.5
V
VPP
Output voltage
12
80
V
VIH
High-level input voltage
VDD -0.5V
V
V
IL
Low-level input voltage
0
0.5
V
fCLK
Clock frequency per register
0.001
25
MHz
TA
Operating free-air temperature
-40
+85
°C
Notes: Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, Enable, etc.) to a known state.
4. Apply VPP.
5. The VPP should not drop below VDD or float during operation.
Power-down sequence should be the reverse of the above.
The VPP should not drop below VDD during operation.
Recommended Operating Conditions



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